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260 条记录 (耗时 0.028 秒)

    Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
    101.
    发明授权
    Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits 失效
    用于在半导体集成电路上制作自对准触点（SAC）的双间隔技术

    公开(公告)号：US6165880A

    公开(公告)日：2000-12-26

    申请号：US94869

    申请日：1998-06-15

    申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

    发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

    IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/32053

    摘要： A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

    摘要翻译： 实现了对图案化多晶硅层（例如FET的栅电极）进行改进的自对准接触（SAC）的方法。 植入轻掺杂的源极/漏极区域。 沉积第二绝缘层并回蚀刻以形成第一侧壁间隔物。 沉积氮化硅蚀刻停止层和第一多晶硅化硅（IPO1）层。 在IPO1层中蚀刻第一SAC开口到蚀刻停止层，同时蚀刻用于栅电极的开口，从而消除掩模步骤。 在SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，其在接触的BOE清洁期间保护第一侧壁间隔物。 使用图案化的多晶硅化合物层来制造SAC和电互连。 沉积第二个IPO层以提供绝缘，并且沉积层间电介质层。 将第二SAC开口蚀刻到蚀刻停止层以进行下一级金属互连，同时蚀刻到栅电极的接触开口以完成。 在第二SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，以在清洁期间保护第一侧壁间隔物。 金属插塞由第二SAC开口中的第一金属和与栅电极的开口形成。 图案化第二金属以将结构完成到第一级金属互连。

    Backside structure for BSI image sensor
    102.
    发明授权
    Backside structure for BSI image sensor 有权
    BSI图像传感器的背面结构

    公开(公告)号：US09356058B2

    公开(公告)日：2016-05-31

    申请号：US13597007

    申请日：2012-08-28

    申请人： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Keng-Yu Chou ,  Shuang-Ji Tsai ,  Min-Feng Kao

    发明人： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Keng-Yu Chou ,  Shuang-Ji Tsai ,  Min-Feng Kao

    IPC分类号： H01L21/311 ,  H01L27/146

    CPC分类号： H01L27/1462 ,  H01L27/1464 ,  H01L27/14685

    摘要： An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming an etching stop layer over the anti-reflective coating, forming a buffer oxide over the etching stop layer, and selectively removing a portion of the buffer oxide through etching, the etching stop layer protecting the anti-reflective coating during the etching. An embodiment image sensor includes a semiconductor disposed in an array region and in a periphery region, the semiconductor supporting a photodiode in the array region, an anti-reflective coating disposed over a surface of the semiconductor, an etching stop layer disposed over the anti-reflective coating, a thickness of the etching stop layer over the photodiode in the array region less than a thickness of the etching stop layer in the periphery region, and a buffer oxide disposed over the etching stop layer in the periphery region.

    摘要翻译： 用于形成图像传感器的实施例方法包括在支撑光电二极管的半导体的表面上形成抗反射涂层，在抗反射涂层上形成蚀刻停止层，在蚀刻停止层上形成缓冲氧化物，并且选择性地去除 通过蚀刻的缓冲氧化物的一部分，在蚀刻期间保护抗反射涂层的蚀刻停止层。 一种实施方式的图像传感器包括：配置在阵列区域和外围区域中的半导体，支撑阵列区域中的光电二极管的半导体，设置在半导体表面上的抗反射涂层， 在阵列区域中的光电二极管上的蚀刻停止层的厚度小于周边区域中的蚀刻停止层的厚度，以及设置在周边区域的蚀刻停止层上的缓冲氧化物。

    Pad design for backside illuminated image sensor
    105.
    发明授权
    Pad design for backside illuminated image sensor 有权
    背面照明图像传感器的垫设计

    公开(公告)号：US09142586B2

    公开(公告)日：2015-09-22

    申请号：US12708167

    申请日：2010-02-18

    申请人： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

    发明人： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

    IPC分类号： H01L27/14 ,  H01L27/146

    CPC分类号： H01L27/14636 ,  H01L23/481 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14683

    摘要： A semiconductor image sensor device includes first and second semiconductor substrates. A pixel array and a control circuit are formed in a first surface of the first substrate. An interconnect layer is formed over the first surface of the first substrate and electrically connects the control circuit to the pixel array. A top conducting layer is formed over the interconnect layer to have electrical connectivity with at least one of the control circuit or the pixel array via the interconnect layer. A surface of a second substrate is bonded to the top conducting layer. A conductive through-silicon-via (TSV) passes through the second substrate, and has electrical connectivity with the top conducting layer. A terminal is formed on an opposite surface of the second substrate, and electrically connected to the TSV.

    摘要翻译： 半导体图像传感器装置包括第一和第二半导体衬底。 像素阵列和控制电路形成在第一基板的第一表面中。 在第一基板的第一表面上形成互连层，并将控制电路电连接到像素阵列。 顶部导电层形成在互连层上，以经由互连层与至少一个控制电路或像素阵列电连接。 第二基板的表面接合到顶部导电层。 导电硅通孔（TSV）通过第二衬底，并且与顶部导电层具有电连接性。 端子形成在第二基板的相对表面上，并电连接到TSV。

    CMOS image sensor chips with stacked scheme and methods for forming the same
    107.
    发明授权
    CMOS image sensor chips with stacked scheme and methods for forming the same 有权
    具有堆叠方案的CMOS图像传感器芯片及其形成方法

    公开(公告)号：US08957358B2

    公开(公告)日：2015-02-17

    申请号：US13571184

    申请日：2012-08-09

    申请人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    发明人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14634 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

    摘要： A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via.

    摘要翻译： 一种设备包括其中包括图像传感器的图像传感器芯片。 一个读出的芯片是底层的，并粘贴到图像传感器芯片上。 读出芯片包括从基本上由复位晶体管，源极跟随器，行选择器及其组合组成的组中选择的逻辑器件。 逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。 外围电路芯片是底层的，并与读出的芯片结合。 外围电路芯片包括逻辑电路，穿透外围电路芯片的半导体衬底的贯通孔以及外围电路芯片底面的电连接器。 电连接器通过通孔电耦合到外围电路芯片中的逻辑电路。

    Multiple gate dielectric structures and methods of forming the same
    108.
    发明授权
    Multiple gate dielectric structures and methods of forming the same 有权
    多栅电介质结构及其形成方法

    公开(公告)号：US08685820B2

    公开(公告)日：2014-04-01

    申请号：US13207643

    申请日：2011-08-11

    申请人： Hsiao-Hui Tseng ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-I Hsu ,  Min-Feng Kao

    发明人： Hsiao-Hui Tseng ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-I Hsu ,  Min-Feng Kao

    IPC分类号： H01L21/336

    CPC分类号： H01L27/14614 ,  H01L27/14689

    摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.

    摘要翻译： 本公开提供了多栅极电介质半导体结构和形成这种结构的方法。 在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。 该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层 栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。