公开(公告)号：US06583632B2

公开(公告)日：2003-06-24

申请号：US09767392

申请日：2001-01-23

申请人： Paul-Werner Von Basse ,  Josef Willer

发明人： Paul-Werner Von Basse ,  Josef Willer

IPC分类号： G01R2726

CPC分类号： G06K9/0002 ,  G01R27/2605

摘要： A grid of capacitor surfaces is connected to read lines and control lines. The read lines are connected alternately to the output of a feedback operational amplifier and to a collecting capacitor. The capacitances to be measured are charged repeatedly and the charges are collected on the collecting capacitors. Between the charging operations, the potential on the read lines is kept constant through the use of the low-resistance output of the operational amplifier. The use of this method in the case of a fingerprint sensor makes it possible to evaluate all the read lines together.

摘要翻译： 电容器表面的栅格连接到读取线和控制线。 读取线交替地连接到反馈运算放大器的输出端和集电电容器。 要测量的电容重复充电，并将电荷收集在收集电容器上。 在充电操作之间，通过使用运算放大器的低电阻输出，读取线路上的电位保持不变。 在指纹传感器的情况下使用该方法可以将所有的读取行一起评估。

公开(公告)号：US06518613B2

公开(公告)日：2003-02-11

申请号：US09968304

申请日：2001-10-01

申请人： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

发明人： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

摘要翻译： 存储单元的MOS晶体管和与其连接的位线设置在基板的第一表面上。 存储单元的电容器设置在基板的第二表面上，第二表面与第一表面相对。 接触件设置在衬底中并将电容器连接到MOS晶体管。

公开(公告)号：US06309930B1

公开(公告)日：2001-10-30

申请号：US09708636

申请日：2000-11-09

申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

IPC分类号： H01L21336

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.

摘要翻译： SRAM单元布置包括每个存储单元的六个MOS晶体管，其被形成为垂直晶体管。 MOS晶体管布置在沟槽（G1，G2，G4）的侧壁处。 诸如例如形成隔离物的栅极（Ga2，Ga4）或导电结构（L3）的存储单元的部分通过布置在衬底的表面（O）上方的相邻的水平导电结构（H5）接触 S）。 存储器单元的部分之间的连接经由经由扩散区（D2）布置在凹陷和字线（W）的侧壁处的第三导电结构（L3），其经由衬底（S）内的凹陷的侧壁相邻的经由 通过相对于垂直于表面（O）的轴线以不同高度部分布置的第二位线（B2）或/和经由导电结构（L1，L2，L6）的第一位线。 触点（K5）同时接触MOS晶体管的多个部分。

公开(公告)号：US6125050A

公开(公告)日：2000-09-26

申请号：US335365

申请日：1999-06-17

申请人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul-Werner Basse ,  Wolfgang Krautschneider

发明人： Franz Hofmann ,  Josef Willer ,  Hans Reisinger ,  Paul-Werner Basse ,  Wolfgang Krautschneider

IPC分类号： H01L27/112 ,  G11C5/02 ,  H01L21/8246

CPC分类号： H01L27/0207 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/11803

摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.

摘要翻译： 平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。 多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。 每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

公开(公告)号：US5500385A

公开(公告)日：1996-03-19

申请号：US451534

申请日：1995-05-26

申请人： Hermann Wendt ,  Josef Willer ,  Hans Reisinger ,  Volker Lehmann

发明人： Hermann Wendt ,  Josef Willer ,  Hans Reisinger ,  Volker Lehmann

IPC分类号： H01L27/04 ,  H01L21/225 ,  H01L21/334 ,  H01L21/822 ,  H01L21/762

CPC分类号： H01L29/66181 ,  Y10S438/924 ,  Y10S438/928 ,  Y10S438/977

摘要： For manufacturing a silicon capacitor, hole openings are produced in an n-doped silicon substrate, a p.sup.+ -doped region is formed at the surface thereof and this surface is provided with a dielectric layer together with a conductive layer. The silicon substrate is thinned with an etching proceeding from the back side, this etching attacking silicon selectively to p.sup.+ -doped silicon and therefore stopping when the p.sup.+ -doped region is reached.

摘要翻译： 为了制造硅电容器，在n掺杂硅衬底中产生孔开口，在其表面形成p +掺杂区域，并且该表面与导电层一起设置介电层。 硅衬底通过从背面进行的蚀刻变薄，该蚀刻选择性地攻击到p +掺杂的硅，因此当达到p +掺杂区域时停止。

公开(公告)号：US07940575B2

公开(公告)日：2011-05-10

申请号：US12058191

申请日：2008-03-28

申请人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

发明人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C16/06

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

摘要翻译： 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

公开(公告)号：US07767567B2

公开(公告)日：2010-08-03

申请号：US11541404

申请日：2006-09-29

申请人： Josef Willer ,  Franz Hofmann

发明人： Josef Willer ,  Franz Hofmann

IPC分类号： H01L21/3205

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.

摘要翻译： 存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。 在为源极线提供的区域中的间隔件之间形成开口。 施加牺牲层以填充开口并且随后被图案化。 间隙填充有介电材料的平坦化层。 去除牺牲层的残余物并施加导电材料以形成源极线。

公开(公告)号：US20090244949A1

公开(公告)日：2009-10-01

申请号：US12058191

申请日：2008-03-28

申请人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

发明人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

IPC分类号： G11C5/06

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

摘要翻译： 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

公开(公告)号：US20090072274A1

公开(公告)日：2009-03-19

申请号：US11855695

申请日：2007-09-14

申请人： Roman Knoefler ,  Michael Specht ,  Josef Willer

发明人： Roman Knoefler ,  Michael Specht ,  Josef Willer

IPC分类号： H01L27/10 ,  H01L21/8238

CPC分类号： H01L27/11568 ,  H01L21/823828 ,  H01L27/105 ,  H01L27/11573

摘要： An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

摘要翻译： 公开了一种包括第一栅极堆叠和第二栅极堆叠的集成电路及其制造方法。 一个实施例提供包括在半导体衬底的主表面的第一表面部分上的第一栅极堆叠和栅极电介质的非易失性存储器单元，以及包括在第二表面部分上的存储层堆叠的第二栅极堆叠。 将第一图案转移到第一栅极堆叠中，将第二图案转移到第二栅极堆叠中。

公开(公告)号：US07416976B2

公开(公告)日：2008-08-26

申请号：US11217122

申请日：2005-08-31

申请人： Josef Willer ,  Patrick Haibach ,  Christoph Andreas Kleint ,  Nicolas Nagel

发明人： Josef Willer ,  Patrick Haibach ,  Christoph Andreas Kleint ,  Nicolas Nagel

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11568

摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

摘要翻译： 半导体产品包括具有基板表面的基板。 多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。 在字线之间提供多个导电接触结构。 该产品还包括多个填充结构。 每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。 两个相应的接触结构在第一方向上彼此间隔一定距离。 在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。 衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。