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    Through-substrate interconnect fabrication methods and resulting structures and assemblies
    104.
    发明申请
    Through-substrate interconnect fabrication methods and resulting structures and assemblies 有权
    通过衬底互连制造方法和所得到的结构和组件

    公开(公告)号：US20060046468A1

    公开(公告)日：2006-03-02

    申请号：US11138544

    申请日：2005-05-26

    申请人： Salman Akram ,  Kyle Kirby

    发明人： Salman Akram ,  Kyle Kirby

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13024 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： A method for forming a conductive via or through-wafer interconnect (TWI) in a semiconductive substrate for use as a contact card, test connector, semiconductor package interposer, or die interconnect includes the acts of (a) forming an oxide or nitride layer on both sides of the substrate, (b) forming a precursor aperture in the substrate at a desired location by laser or etch, (c) further etching the precursor aperture to enlarge and shape at least a portion thereof with undercut portions below an initial etch mask layer, (d) lining the aperture with a passivation material, (e) filling the aperture with a conductive material, and (f) thinning one or both surfaces of the substrate to achieve desired stand-off distances of the opposed via ends. The shaped via aperture has an enlarged central portion, and one or more end portions which taper to smaller end surfaces. The one or more via end portions may be trapezoidal in shape. A further rounding etch act following the shaping etch will result in rounded, i.e. a frustoconical shape. The shape is conducive to improved solder ball/bump attachment, and enables forming vias of very small diameter and pitch.

    摘要翻译： 用于形成用于接触卡，测试连接器，半导体封装插入件或管芯互连的半导体衬底中的导电通孔或贯穿晶片互连（TWI）的方法包括以下动作：（a）在 （b）通过激光或蚀刻在所需位置在衬底中形成前体孔，（c）进一步蚀刻前体孔，以在初始蚀刻掩模下面的底切部分扩大和形成其至少一部分 层，（d）用钝化材料衬套孔，（e）用导电材料填充孔，以及（f）使衬底的一个或两个表面变薄以实现相对的通孔端的期望的间隔距离。 成形的通孔具有扩大的中心部分，以及一个或多个锥形到较小端面的端部。 一个或多个通孔端部可以是梯形的形状。 在成形蚀刻之后的进一步的圆化蚀刻行为将导致圆形，即截头圆锥形状。 该形状有利于改善焊球/凸块附着，并且能够形成非常小的直径和间距的通孔。

    Packaged microelectronic imagers and methods of packaging microelectronic imagers
    106.
    发明申请
    Packaged microelectronic imagers and methods of packaging microelectronic imagers 有权
    封装的微电子成像器和包装微电子成像器的方法

    公开(公告)号：US20050184219A1

    公开(公告)日：2005-08-25

    申请号：US10785466

    申请日：2004-02-23

    申请人： Kyle Kirby

    发明人： Kyle Kirby

    IPC分类号： H01L27/00 ,  H01L31/0203

    CPC分类号： H01L27/14618 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

    摘要： Microelectronic imagers and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a plurality of terminals electrically coupled to the integrated circuit. The microelectronic imager can further include a single unitary member cover unit having a window and a side member projecting from the window. The side member is attached to the die. A plurality of electrically conductive interconnects can extend through the microelectronic die and/or the cover unit and are electrically coupled to corresponding terminals. The microelectronic imager can further include an optics unit having an optic member attached to the cover unit, with the optic member positioned at a desired location relative to the image sensor.

    摘要翻译： 本文公开了微电子成像器和包装微电子成像器的方法。 在一个实施例中，微电子成像器可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路，以及电耦合到集成电路的多个端子。 微电子成像器还可以包括具有窗口和从窗口突出的侧部构件的单个整体构件盖单元。 侧构件附接到模具。 多个导电互连可以延伸通过微电子管芯和/或盖单元并且电耦合到相应的端子。 微电子成像器还可以包括具有连接到盖单元的光学构件的光学单元，其中光学构件相对于图像传感器定位在期望位置。

    PROBE CARD FOR USE WITH MICROELECTRONIC COMPONENTS,AND METHODS FOR MAKING SAME
    109.
    发明申请
    PROBE CARD FOR USE WITH MICROELECTRONIC COMPONENTS,AND METHODS FOR MAKING SAME 失效
    用微电子元件使用的探针卡及其制造方法

    公开(公告)号：US20050046431A1

    公开(公告)日：2005-03-03

    申请号：US10653766

    申请日：2003-09-03

    申请人： Kyle Kirby

    发明人： Kyle Kirby

    IPC分类号： G01R3/00 ,  G01R31/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/42 ,  G01R31/02

    CPC分类号： G01R31/2886 ,  G01R3/00 ,  H01L2924/15184 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/0969 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49126

    摘要： The present disclosure provides probe cards which may be used for testing microelectronic components, including methods of making and using such probe cards. One exemplary implementation provides a probe card that employs a substrate with a plurality of openings. A first probe, which may be used to contact a microelectronic component, includes a first conductor slidably received in one of the openings and a first electrical trace. The electrical trace may be patterned from a metal layer on the back of the substrate and include a resilient free length adapted to urge the first conductor to extend outwardly beyond the front of the substrate. A second probe includes a second conductor slidably received in another one of the openings and a second electrical trace. The second electrical trace may be patterned from a metal layer on the front of the substrate and include a resilient free length adapted to urge the second conductor to extend outwardly beyond the back of the substrate. An electrical pathway through the substrate may electrically couple and first and second electrical traces.

    摘要翻译： 本公开提供了可用于测试微电子部件的探针卡，包括制造和使用这种探针卡的方法。 一个示例性实施例提供了采用具有多个开口的基板的探针卡。 可用于接触微电子部件的第一探针包括可滑动地容纳在一个开口中的第一导体和第一电迹线。 电迹线可以从衬底的背面上的金属层图案化，并且包括适于促使第一导体向外延伸超出衬底前部的弹性自由长度。 第二探针包括可滑动地容纳在另一个开口中的第二导体和第二电迹线。 第二电迹线可以从衬底前面的金属层图案化，并且包括适于促使第二导体向外延伸超过衬底背面的弹性自由长度。 穿过衬底的电路可以电耦合和第一和第二电迹线。

    Method for increasing etch rate during deep silicon dry etch
    110.
    发明授权
    Method for increasing etch rate during deep silicon dry etch 有权
    在深硅干蚀刻中提高蚀刻速率的方法

    公开(公告)号：US08110488B2

    公开(公告)日：2012-02-07

    申请号：US12434882

    申请日：2009-05-04

    申请人： Kyle Kirby ,  Swarnal Borthakur

    发明人： Kyle Kirby ,  Swarnal Borthakur

    IPC分类号： H01L21/38

    CPC分类号： H01L21/76898 ,  H01L21/3083

    摘要： A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.

    摘要翻译： 提出了通过改变蚀刻掩模的几何形状在深硅干蚀刻期间提高蚀刻速率的方法。 通过稍微改变蚀刻掩模的形状，在使用椭圆形蚀刻掩模的一个区域中，与使用不同几何形状的蚀刻掩模的其它区域相比，即使露出几乎相同量的硅，蚀刻速率增加。 此外，可以通过使用不同的几何形状的蚀刻掩模来控制通孔的深度，同时保持所有通孔的直径几乎相同的尺寸。