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公开(公告)号：US10777291B2
公开(公告)日：2020-09-15
申请号：US16284491
申请日：2019-02-25
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Hongmei Wang
Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
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公开(公告)号：US10777266B2
公开(公告)日：2020-09-15
申请号：US16185146
申请日：2018-11-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US10665298B2
公开(公告)日：2020-05-26
申请号：US16419821
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US10593730B1
公开(公告)日：2020-03-17
申请号：US16156194
申请日：2018-10-10
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Redaelli , Agostino Pirovano
Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
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公开(公告)号：US10559337B1
公开(公告)日：2020-02-11
申请号：US16206006
申请日：2018-11-30
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
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Patent Agency Ranking
公开(公告)号：US10418119B2
公开(公告)日：2019-09-17
申请号：US15691465
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
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公开(公告)号：US20190189203A1
公开(公告)日：2019-06-20
申请号：US15842496
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20190140174A1
公开(公告)日：2019-05-09
申请号：US16184314
申请日：2018-11-08
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto M. Meotto
CPC classification number: H01L45/1286 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C13/04 , G11C2013/008 , G11C2213/56 , G11C2213/76 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1608
Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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公开(公告)号：US20190036022A1
公开(公告)日：2019-01-31
申请号：US15660829
申请日：2017-07-26
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
CPC classification number: H01L45/1675 , H01L27/2409 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/141
Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US20190006006A1
公开(公告)日：2019-01-03
申请号：US16105874
申请日：2018-08-20
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Innocenzo Tortorelli , Andrea Redaelli , Fabio Pellizzer
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C13/0097 , G11C2013/0052 , G11C2013/0073 , G11C2013/0092 , G11C2213/73 , G11C2213/76
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
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