公开(公告)号：US11704028B2

公开(公告)日：2023-07-18

申请号：US17692683

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/14 ,  G11C16/34 ,  G06F1/3206

CPC classification number: G06F3/0619 ,  G06F1/3206 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/076 ,  G06F11/1471 ,  G11C16/3404

Abstract: Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).

公开(公告)号：US11694760B2

公开(公告)日：2023-07-04

申请号：US17382926

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  John Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

CPC classification number: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/886

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US11513889B2

公开(公告)日：2022-11-29

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11488670B2

公开(公告)日：2022-11-01

申请号：US17181826

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Jung Sheng Hoei ,  Harish Reddy Singidi ,  Ting Luo ,  Ankit Vinod Vashi

IPC: G11C16/10 ,  G11C16/34 ,  G11C7/04

Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

公开(公告)号：US20220270702A1

公开(公告)日：2022-08-25

申请号：US17743989

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Ting Luo ,  Chun Sum Yueng

IPC: G11C29/42 ,  G11C7/20 ,  G11C29/44

Abstract: A method includes determining whether a data reliability parameter associated with a set of memory cells is greater than a threshold data reliability parameter and in response to determining that the data reliability parameter is greater than the threshold data reliability parameter, performing an error recovery operation. The method further includes, subsequent to performing the error recovery operation, determining whether the data reliability parameter associated with the set of memory cells is less than the threshold data reliability parameter and in response to determining that the data reliability parameter is less than the threshold data reliability parameter, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.

公开(公告)号：US20210350871A1

公开(公告)日：2021-11-11

申请号：US17382926

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  Xu Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US20210193231A1

公开(公告)日：2021-06-24

申请号：US16807739

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Chun Sum Yeung

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/10

Abstract: A processing device, operatively coupled with the memory device, is configured to receive a read request identifying data stored in a data unit of the memory device. The processing device further identifies a set of data units with which the data unit is associated, the set of data units is one of a plurality of sets of data units, and each data unit in the set of data units was programmed within a period of time associated with the set of data units. The processing device also determines a read voltage level of the set of data units, each of the plurality of sets of data units has a separate read voltage level. The processing device further performs a read operation on the data unit of the memory device using the read voltage level of the set of data units.

公开(公告)号：US10777284B2

公开(公告)日：2020-09-15

申请号：US16782720

申请日：2020-02-05

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C29/02 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20200212935A1

公开(公告)日：2020-07-02

申请号：US16235171

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo

IPC: H03M13/11 ,  G06F11/10

Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.

公开(公告)号：US10685731B2

公开(公告)日：2020-06-16

申请号：US16410764

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Allen Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G06F11/07 ,  G11C29/50 ,  G06F11/10

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.