公开(公告)号：US10910399B2

公开(公告)日：2021-02-02

申请号：US16353028

申请日：2019-03-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L29/06 ,  H01L21/762 ,  H01L21/28

Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.

公开(公告)号：US10891077B2

公开(公告)日：2021-01-12

申请号：US16232119

申请日：2018-12-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hang-Ting Lue ,  Yuan-Hao Chang

IPC: G06F3/06

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

公开(公告)号：US10790028B1

公开(公告)日：2020-09-29

申请号：US16576652

申请日：2019-09-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Lee-Yin Lin

IPC: G11C16/24 ,  G11C5/02 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06

Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.

公开(公告)号：US10388720B2

公开(公告)日：2019-08-20

申请号：US15279203

申请日：2016-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh

IPC: H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

公开(公告)号：US20190148393A1

公开(公告)日：2019-05-16

申请号：US16037281

申请日：2018-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/11556 ,  H01L27/06 ,  H01L27/108 ,  H01L27/112 ,  G11C16/04 ,  G11C11/4097 ,  H01L21/822

Abstract: A device comprises a 3D array of cells arranged for execution of a sum-of-products operation, the cells in the 3D array disposed in cross-points of a plurality of vertical lines and a plurality of horizontal lines, the cells having programmable conductances. A gate driver is coupled to gate lines which applies control gate voltages which in combination with the programmable conductances of the cells correspond to weights Wxyz of terms in the sum-of-products operation. An input driver applies voltages to cells in the array corresponding to input variables Xy. A sensing circuit senses a sum of currents from cells in the 3D array corresponding to the sum-of-products.

公开(公告)号：USRE47311E1

公开(公告)日：2019-03-19

申请号：US15210751

申请日：2016-07-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Erh-Kun Lai

IPC: H01L23/52 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11578 ,  H01L27/11531 ,  H01L27/11524

Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

公开(公告)号：US20180175051A1

公开(公告)日：2018-06-21

申请号：US15379527

申请日：2016-12-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L27/11582 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L27/1157

Abstract: A 3D memory device includes a substrate, a ridge-shaped stack, a memory layer, a channel layer and a capping layer. The ridge-shaped stack includes a plurality of conductive strips extending along a first direction and stacked on the substrate. The memory layer is stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight with the first direction. The channel layer is stacked on the memory layer along the second direction and has a narrow sidewall having a long side extending along the first direction. The capping layer is stacked on the narrow sidewall along a third direction that forms a non-straight angle with the second direction.

公开(公告)号：US09831257B2

公开(公告)日：2017-11-28

申请号：US15017487

申请日：2016-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/11 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11521 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11582 ,  H01L28/00

Abstract: A memory device is provided that includes a plurality of memory cells. The memory device includes a plurality of stacks of conductive strips separated by insulating strips. Data storage structures including floating gates are disposed along the conductive strips in the stacks. Vertical channel films are disposed on sidewalls of the stacks. Memory cells in the plurality of memory cells have channels in the vertical channel films, and control gates in the conductive strips. A tunnel oxide layer is disposed between the vertical channel films and the floating gates. The floating gates can be coplanar with conductive strips in the plurality of stacks, or be disposed between the conductive strips in the plurality of stacks.

公开(公告)号：USRE46522E1

公开(公告)日：2017-08-22

申请号：US14602158

申请日：2015-01-21

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C16/00 ,  H01L29/792 ,  G11C16/34 ,  H01L29/66 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11578

CPC classification number: H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

公开(公告)号：US09461175B2

公开(公告)日：2016-10-04

申请号：US14209962

申请日：2014-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: G11C16/04 ,  H01L29/786 ,  H01L29/423 ,  H01L29/739 ,  H01L27/092 ,  H01L29/66 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase.

Abstract translation: 存储器结构包括具有多栅极沟道区的半导体条，与沟道区的第一侧相邻的p型端子区和与沟道区的第二侧相邻的n型端子区。 多个字线布置成在沟道区域的交叉点处穿过半导体条。 位线耦合到半导体条的第一端，并且参考线耦合到半导体条的第二端。 电荷存储结构设置在多个字线中的字线和半导体条的沟道区之间，由此存储单元沿着位线和参考线之间的半导体条串联设置。 可以使用偏移未选择的字线来选择单个所选单元格中的n沟道或p沟道模式进行读取，编程或擦除。