公开(公告)号：US20070063306A1

公开(公告)日：2007-03-22

申请号：US11234014

申请日：2005-09-22

申请人： Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Robert Chau

发明人： Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Robert Chau

IPC分类号： H01L27/095

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/2022 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/785

摘要： Embodiments of the invention provide a substrate with a surface having different crystal orientations in different areas. Embodiments of the invention provide a substrate with a portion having a crystal orientation and another portion having a crystal orientation. N— and P-type devices may both be formed on the substrate, with each type of device having the proper crystal orientation for optimum performance.

摘要翻译： 本发明的实施例提供一种具有在不同区域中具有不同晶体取向的表面的基底。 本发明的实施方案提供了具有<100>晶体取向的部分和具有<110>晶体取向的另一部分的基底。 可以在衬底上形成N型和P型器件，每种类型的器件具有适当的晶体取向以实现最佳性能。

公开(公告)号：US20070001173A1

公开(公告)日：2007-01-04

申请号：US11158661

申请日：2005-06-21

申请人： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau ,  Brian Doyle

发明人： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau ,  Brian Doyle

IPC分类号： H01L29/10

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US20050095792A1

公开(公告)日：2005-05-05

申请号：US10696204

申请日：2003-10-29

申请人： Ying Zhou ,  Matthew Metz ,  Justin Brask ,  John Burghard ,  Markus Kuhn ,  Suman Datta ,  Robert Chau

发明人： Ying Zhou ,  Matthew Metz ,  Justin Brask ,  John Burghard ,  Markus Kuhn ,  Suman Datta ,  Robert Chau

IPC分类号： H01L21/316 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02282 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/316

摘要： A dielectric deposited on a substrate may be exposed to a salt solution. While exposed to the salt solution, an oxide is deposited on the dielectric.

摘要翻译： 沉积在基底上的电介质可以暴露于盐溶液中。 当暴露于盐溶液时，在电介质上沉积氧化物。

公开(公告)号：US20060071275A1

公开(公告)日：2006-04-06

申请号：US10956279

申请日：2004-09-30

申请人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20060138552A1

公开(公告)日：2006-06-29

申请号：US11360269

申请日：2006-02-22

申请人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20070158702A1

公开(公告)日：2007-07-12

申请号：US11322827

申请日：2005-12-30

申请人： Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Gilbert Dewey

发明人： Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Gilbert Dewey

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/785 ,  H01L29/4908

摘要： A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.

摘要翻译： 一种晶体管，包括：半导体，包括源极，漏极和介于源极和漏极之间的沟道; 具有第一厚度的第一介电层，所述第一介电层位于所述通道上; 具有第二厚度的第二介电层，所述第二介电层位于所述第一介电层上; 以及第二介质层上的栅电极，其中晶体管栅极由中间间隙金属制成。 一种方法，包括在半导体层的至少一个表面上沉积第一介电层; 在所述第一电介质层上沉积第二电介质层; 在所述第二电介质层上沉积中间间隙金属层; 以及对第一电介质层，第二电介质层和中间间隙金属层进行图案化和蚀刻以产生通过第一电介质和第二电介质与衬底分离的栅电极。 公开和要求保护其他实施例。

公开(公告)号：US20070145498A1

公开(公告)日：2007-06-28

申请号：US11320305

申请日：2005-12-27

申请人： Matthew Metz ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66636

摘要： Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.

摘要翻译： 本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。 在高k栅极电介质层和金属栅极的侧壁上的氧气清除间隔层可以在高温过程中减少这种氧化。

公开(公告)号：US07608883B2

公开(公告)日：2009-10-27

申请号：US12072971

申请日：2008-02-28

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/76

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20060223243A1

公开(公告)日：2006-10-05

申请号：US11095829

申请日：2005-03-30

申请人： Marko Radosavljevic ,  Justin Brask ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau

发明人： Marko Radosavljevic ,  Justin Brask ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L51/105 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： A metal to Carbon nanotube contact region is described that comprises a chemical bond between the metal and the Carbon nanotube.

摘要翻译： 描述了金属与碳纳米管接触区域，其包括金属和碳纳米管之间的化学键。

公开(公告)号：US07342277B2

公开(公告)日：2008-03-11

申请号：US11285763

申请日：2005-11-21

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/76

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.