公开(公告)号：US10359933B2

公开(公告)日：2019-07-23

申请号：US15269518

申请日：2016-09-19

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0893 ,  G06F12/02 ,  G06F12/0888 ,  G06F11/34

Abstract: A memory having a memory controller is configured to operate a hybrid cache including a dynamic cache including x-level cell (XLC) (e.g., multi-level cell (MLC)) blocks and a static cache including single level cell (SLC) blocks. A method of operating the memory includes storing at least a portion of host data into the SLC blocks as static cache; and storing at least another portion of host data into XLC blocks in an SLC mode as dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. At least one of the static cache or dynamic cache may be disabled based on monitoring a workload of the hybrid cache relative to a Total Bytes Written (TBW) specification, such as by counting program-erase (PE) cycles of different portions of memory, or responsive to the workload exceeding a predetermined threshold defining one or more switch points.

公开(公告)号：US20190130981A1

公开(公告)日：2019-05-02

申请号：US16129497

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Ting Luo ,  Ashutosh Malshe ,  Preston Thomson ,  Jianmin Huang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G06F1/16 ,  G06F1/30 ,  G11C29/02

CPC classification number: G11C16/3404 ,  G06F1/1635 ,  G06F1/305 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028

Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.

公开(公告)号：US20190043592A1

公开(公告)日：2019-02-07

申请号：US16127085

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Peng Fei ,  Michael G. Miller ,  Roland J. Awusie ,  Kishore Kumar Muchherla ,  Renato C. Padilla ,  Harish R. Singidi ,  Jung Sheng Hoei ,  Gianni S. Alsasua

IPC: G11C16/28

CPC classification number: G11C16/28 ,  G11C29/00 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/2254

Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.

公开(公告)号：US10199111B1

公开(公告)日：2019-02-05

申请号：US15669055

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Peng Fei ,  Michael G. Miller ,  Roland J. Awusie ,  Kishore Kumar Muchherla ,  Renato C. Padilla ,  Harish R. Singidi ,  Jung Sheng Hoei ,  Gianni S. Alsasua

IPC: G11C16/10 ,  G11C16/28

Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.

公开(公告)号：US10121551B1

公开(公告)日：2018-11-06

申请号：US15693002

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Singidi ,  Ting Luo ,  Ashutosh Malshe ,  Preston Thomson ,  Jianmin Huang

IPC: G11C16/06 ,  G11C16/34 ,  G06F1/30 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G06F1/16

Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.

公开(公告)号：US20180293001A1

公开(公告)日：2018-10-11

申请号：US15479356

申请日：2017-04-05

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0634 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G11C16/00

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.