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    THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE
    102.
    发明申请
    THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE 有权

    公开(公告)号：US20160156457A1

    公开(公告)日：2016-06-02

    申请号：US15013003

    申请日：2016-02-02

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley

    IPC: H04L7/033 ,  H04L25/49

    CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

    Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

    ADJUSTING APPLICATION PARAMETERS FOR INTERFERENCE MITIGATION
    103.
    发明申请
    ADJUSTING APPLICATION PARAMETERS FOR INTERFERENCE MITIGATION 有权
    调整干扰减轻的应用参数

    公开(公告)号：US20160087732A1

    公开(公告)日：2016-03-24

    申请号：US14494998

    申请日：2014-09-24

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic Wietfeldt ,  George Chrisikos ,  George Alan Wiley

    IPC: H04B15/02 ,  H04B17/23

    CPC classification number: H04B15/02 ,  H04B1/123 ,  H04B17/23 ,  H04W72/082

    Abstract: Aspects of adjusting application parameters for interference mitigation are disclosed. In one aspect, a computing device is provided that employs a control system configured to detect and mitigate electromagnetic interference (EMI) generated within the computing device. More specifically, the control system is configured to detect possible EMI conditions and adjust parameters within the computing device to mitigate such EMI. In this manner, the computing device includes an aggressor application and a victim receiver. The control system is configured to analyze performance tradeoffs based on an acceptable performance level of the aggressor application and the performance degradation experienced by the victim receiver. Based on such analysis, the control system is configured to adjust parameters associated with the aggressor application to mitigate the EMI. Thus, the control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to the EMI.

    Abstract translation: 公开了调整用于干扰减轻的应用参数的方面。 在一个方面，提供了一种计算设备，其采用配置成检测和减轻在计算设备内产生的电磁干扰（EMI）的控制系统。 更具体地，控制系统被配置为检测可能的EMI条件并且调整计算设备内的参数以减轻这样的EMI。 以这种方式，计算设备包括攻击者应用和受害者接收器。 控制系统被配置为基于攻击者应用的可接受的性能水平和受害者接收器所经历的性能下降来分析性能权衡。 基于这种分析，控制系统被配置为调整与侵略者应用相关联的参数以减轻EMI。 因此，控制系统为设计人员提供了一种附加工具，可以降低由于EMI引起的受害接收机的性能下降。

    MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS
    104.
    发明申请
    MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS 有权
    多线对信号通过配对传播延迟线对

    公开(公告)号：US20150381340A1

    公开(公告)日：2015-12-31

    申请号：US14315142

    申请日：2014-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

    IPC: H04L7/00 ,  H04B3/462 ,  H04B3/54

    CPC classification number: H04L7/0041 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L25/0264

    Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

    Abstract translation: 在包括至少三条电线的多线通道中，多线通道的每条唯一的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

    Three phase clock recovery delay calibration
    105.
    发明授权
    Three phase clock recovery delay calibration 有权
    三相时钟恢复延迟校准

    公开(公告)号：US09137008B2

    公开(公告)日：2015-09-15

    申请号：US14336572

    申请日：2014-07-21

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Chulkyu Lee

    IPC: H04L25/02 ,  H04L7/033 ,  H04B3/02 ,  G06F13/42

    CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04B3/02 ,  H04L7/0004 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0292 ,  Y02D10/14 ,  Y02D10/151

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 时钟恢复电路可以基于在两个或更多个连接器上发送的前置码中的状态转换来校准。 描述校准方法。 该方法包括检测多相信号的前导码中的多个转换并校准延迟元件以提供与多相信号的计时周期匹配的延迟。 每个转换可以仅由多个检测器中的一个检测。 延迟元件可以基于多个转换中的连续检测之间的时间间隔进行校准。

    Multi-phase clock generation method
    106.
    发明授权
    Multi-phase clock generation method 有权
    多相时钟生成方法

    公开(公告)号：US09130735B2

    公开(公告)日：2015-09-08

    申请号：US14336977

    申请日：2014-07-21

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  George Alan Wiley ,  Richard Dominic Wietfeldt

    IPC: H04B3/50 ,  H04L7/00 ,  H04L7/033 ,  G06F13/42

    CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04B3/50 ,  H04L7/00 ,  H04L7/0037 ,  H04L7/0041

    Abstract: Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors, and generating a clock signal by detecting transitions in the received sequence of symbols. The method also comprises delaying the received sequence of symbols, and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols.

    Abstract translation: 本文描述了用于多相信令的系统和方法。 在一个实施例中，一种用于接收数据的方法包括从多个导体接收符号序列，以及通过检测所接收的符号序列中的转变来产生时钟信号。 该方法还包括延迟接收到的符号序列，并使用时钟信号捕获延迟符号序列中的一个或多个符号，其中使用基于时钟信号生成的时钟信号中的时钟脉冲来捕获延迟符号序列中的先前符号 在所接收的符号序列中检测到到当前符号的转换。

    METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE
    107.
    发明申请
    METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE 有权
    使用多个主机在单个主总线架构中运行的方法和装置

    公开(公告)号：US20150074305A1

    公开(公告)日：2015-03-12

    申请号：US14480540

    申请日：2014-09-08

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  Richard Dominic Wietfeldt ,  George Alan Wiley

    IPC: G06F13/362 ,  G06F11/30 ,  G06F13/24

    CPC classification number: G06F13/378 ,  G06F13/24 ,  G06F13/36 ,  G06F13/362 ,  G06F2213/3602

    Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

    Abstract translation: 为了通过支持单个主器件的总线架构来容纳多个主器件，提供了一种用于非活动主器件以通过共享的单线IRQ总线触发IRQ信号的机制。 然后当前主机通过共享数据总线轮询其他无效主设备，以确定哪个无效主设备正在断言IRQ信号。 当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。

    METHOD TO MINIMIZE THE NUMBER OF IRQ LINES FROM PERIPHERALS TO ONE WIRE
    108.
    发明申请
    METHOD TO MINIMIZE THE NUMBER OF IRQ LINES FROM PERIPHERALS TO ONE WIRE 有权
    将外围IRQ线数量最小化为一根线的方法

    公开(公告)号：US20150058507A1

    公开(公告)日：2015-02-26

    申请号：US14462363

    申请日：2014-08-18

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  Richard Dominic Wietfeldt ,  George Alan Wiley

    IPC: G06F13/42 ,  G06F13/24

    CPC classification number: G06F13/4226 ,  G06F13/22 ,  G06F13/24 ,  G06F13/26 ,  G06F2211/001 ,  G06F2211/002

    Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

    Abstract translation: 提供了一个主器件，其耦合到共享单线中断请求（IRQ）总线和控制数据总线。 主设备组从设备将共享单线IRQ总线耦合到一个或多个组中，其中每个组与不同的IRQ信号相关联。 然后，主设备监视IRQ总线以确定至少一个从设备何时确定IRQ信号。 然后，主设备识别与IRQ信号相关联的组。 然后由主设备扫描或查询所识别的组的从设备，以确定哪个从设备在IRQ总线上断言IRQ信号。 每个组使用可区分的IRQ信号来允许主设备确定哪个组进行查询或扫描。

    CAMERA CONTROL INTERFACE EXTENSION BUS
    109.
    发明申请
    CAMERA CONTROL INTERFACE EXTENSION BUS 有权
    摄像机控制界面扩展总线

    公开(公告)号：US20140372643A1

    公开(公告)日：2014-12-18

    申请号：US14302362

    申请日：2014-06-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

    IPC: G06F13/42

    CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

    Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

    Abstract translation: 描述了提供用于内部集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线的改进的性能的系统，方法和装置。 描述CCI扩展（CCIe）设备。 CCIe设备可以配置为总线主机或从机。 在一种方法中，CCIe发射机可以从一组比特生成转换号码，将转换号码转换为符号序列，并以两线串行总线的信令状态发送符号序列。 定时信息可以在符号序列中的连续符号对符号之间的转换中被编码。 例如，每个转换可能导致两线串行总线的至少一根线的信令状态改变。 CCIe接收机可以从转换中导出接收时钟，以便接收和解码符号序列。

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