公开(公告)号：US20240365558A1

公开(公告)日：2024-10-31

申请号：US18763112

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.

公开(公告)号：US12127411B2

公开(公告)日：2024-10-22

申请号：US18363986

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/40 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC classification number: H10B51/30 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US12113063B2

公开(公告)日：2024-10-08

申请号：US18103210

申请日：2023-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N70/00 ,  H10N70/20 ,  H01L21/8234 ,  H10K59/00

CPC classification number: H01L27/0688 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/525 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N70/011 ,  H10N70/20 ,  H10N70/231 ,  H01L21/823475 ,  H10K59/00

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US20240096712A1

公开(公告)日：2024-03-21

申请号：US18152154

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Jiang ,  Chieh-Fang Chen ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/84 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5226 ,  H01L27/1207

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

公开(公告)号：US20240088291A1

公开(公告)日：2024-03-14

申请号：US18510506

申请日：2023-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chang Sun ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  TsuChing Yang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/66 ,  H10B51/00

CPC classification number: H01L29/78391 ,  H01L29/6684 ,  H10B51/00

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

公开(公告)号：US20240079497A1

公开(公告)日：2024-03-07

申请号：US17901843

申请日：2022-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Huang ,  Gao-Ming Wu ,  Katherine H CHIANG ,  Chung-Te Lin

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/0847 ,  H01L29/66742 ,  H01L29/78696

Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

公开(公告)号：US11925030B2

公开(公告)日：2024-03-05

申请号：US17518950

申请日：2021-11-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B41/23 ,  H10B41/27 ,  H10B41/35 ,  H10B43/23 ,  H10B51/20 ,  H10B51/40 ,  H10B51/50

CPC classification number: H10B51/30 ,  H10B41/23 ,  H10B41/27 ,  H10B41/35 ,  H10B43/23 ,  H10B51/20 ,  H10B51/40 ,  H10B51/50

Abstract: Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

公开(公告)号：US20240064993A1

公开(公告)日：2024-02-22

申请号：US17885575

申请日：2022-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Song-Fu Liao ,  Kuo-Chang Chiang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11597 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

公开(公告)号：US11903217B2

公开(公告)日：2024-02-13

申请号：US17394757

申请日：2021-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/00 ,  H01L49/02

CPC classification number: H10B51/30 ,  H01L28/75 ,  H10B51/00 ,  H01L2924/1441

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

公开(公告)号：US20240049470A1

公开(公告)日：2024-02-08

申请号：US17818343

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Jun Wu ,  Sun-Yi Chang ,  Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/11568 ,  H01L27/11521 ,  H01L27/1159 ,  H01L27/22 ,  H01L27/24 ,  G11C16/08 ,  G11C11/22 ,  G11C11/16 ,  G11C13/00

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L27/1159 ,  H01L27/228 ,  H01L27/2436 ,  G11C16/08 ,  G11C11/2257 ,  G11C11/1657 ,  G11C13/0028

Abstract: A memory cell array is provided. The memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. A plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.