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    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    101.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200371937A1

    公开(公告)日：2020-11-26

    申请号：US16879264

    申请日：2020-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F12/0888 ,  G06F12/0811

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
    102.
    发明申请
    PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM 审中-公开

    公开(公告)号：US20200057720A1

    公开(公告)日：2020-02-20

    申请号：US16102862

    申请日：2018-08-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung ONG

    IPC: G06F12/0862 ,  G06F12/0811 ,  G06F9/38

    Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

    ZERO CYCLE CLOCK INVALIDATE OPERATION
    106.
    发明申请
    ZERO CYCLE CLOCK INVALIDATE OPERATION 有权
    零周期无效操作

    公开(公告)号：US20140108737A1

    公开(公告)日：2014-04-17

    申请号：US13649269

    申请日：2012-10-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

    Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data.

    Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并且映射到块无效操作的地址范围内的访问将被作为高速缓存未命中，以确保请求的CPU将接收到有效的数据 。

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