公开(公告)号：US11693661B2

公开(公告)日：2023-07-04

申请号：US17241198

申请日：2021-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Kai Chirca

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

公开(公告)号：US20230185719A1

公开(公告)日：2023-06-15

申请号：US18167921

申请日：2023-02-13

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/0842 ,  G06F12/0811 ,  G06F1/14 ,  G06F12/0888 ,  G06F9/54

CPC classification number: G06F12/0842 ,  G06F12/0811 ,  G06F1/14 ,  G06F12/0888 ,  G06F9/544 ,  G06F2212/1016

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US20230185649A1

公开(公告)日：2023-06-15

申请号：US18164688

申请日：2023-02-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/07 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/36

CPC classification number: G06F11/0772 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3867 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F11/00 ,  G06F11/27 ,  G06F11/073 ,  G06F11/0721 ,  G06F11/3037 ,  G06F11/3648 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/602

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US11675700B2

公开(公告)日：2023-06-13

申请号：US17666196

申请日：2022-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Timothy David Anderson ,  Kai Chirca

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

公开(公告)号：US11422938B2

公开(公告)日：2022-08-23

申请号：US16653139

申请日：2019-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David Pierson ,  Kai Chirca ,  Timothy David Anderson

IPC: G06F12/084 ,  G06F12/0831 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0846 ,  G06F12/0862

Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.

公开(公告)号：US20220244957A1

公开(公告)日：2022-08-04

申请号：US17720657

申请日：2022-04-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F11/00 ,  G06F12/0862 ,  G06F12/1036

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US20220156192A1

公开(公告)日：2022-05-19

申请号：US17589648

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Matthew David Pierson ,  David E. Smith ,  Timothy David Anderson

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

公开(公告)号：US20210406014A1

公开(公告)日：2021-12-30

申请号：US17472877

申请日：2021-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F11/00 ,  G06F12/0831 ,  G06F12/1027

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US11212256B2

公开(公告)日：2021-12-28

申请号：US16786734

申请日：2020-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

IPC: H04L29/06

Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

公开(公告)号：US20210334103A1

公开(公告)日：2021-10-28

申请号：US17367384

申请日：2021-07-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.