公开(公告)号：US10153369B2

公开(公告)日：2018-12-11

申请号：US15627427

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

公开(公告)号：US20180218917A1

公开(公告)日：2018-08-02

申请号：US15423544

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Hon-Huei Liu ,  Chia-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/66

Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.

公开(公告)号：US20180151371A1

公开(公告)日：2018-05-31

申请号：US15880506

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/283 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/31 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/283 ,  H01L21/308 ,  H01L21/31 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/845

Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.

公开(公告)号：US20180144988A1

公开(公告)日：2018-05-24

申请号：US15861692

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.

公开(公告)号：US20180061963A1

公开(公告)日：2018-03-01

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US09837511B2

公开(公告)日：2017-12-05

申请号：US15403187

申请日：2017-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/335 ,  H01L21/225 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.

公开(公告)号：US09837282B1

公开(公告)日：2017-12-05

申请号：US15667641

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen ,  En-Chiuan Liou

IPC: H01L21/02 ,  H01L21/308 ,  H01L21/66 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L22/12 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.

公开(公告)号：US20170323854A1

公开(公告)日：2017-11-09

申请号：US15145789

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L23/544 ,  H01L21/027 ,  H01L21/308 ,  H01L21/66

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system. The overlay of the first layer lithography pattern and the target portion is measured by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system. The first overlay data is fed to form a second layer lithography pattern.

公开(公告)号：US09761460B1

公开(公告)日：2017-09-12

申请号：US15365967

申请日：2016-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen ,  En-Chiuan Liou

IPC: H01L21/02 ,  H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.

公开(公告)号：US09746786B2

公开(公告)日：2017-08-29

申请号：US15260322

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Yi-Jing Wang ,  Chia-Hsun Tseng

IPC: G03F7/00 ,  G03F7/20

CPC classification number: G03F7/70633 ,  H01L21/02642 ,  H01L21/027 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.