公开(公告)号：US07807538B2

公开(公告)日：2010-10-05

申请号：US11898295

申请日：2007-09-11

申请人： Takashi Yamauchi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga

发明人： Takashi Yamauchi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/47 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785

摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.

摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅电极两侧的基板表面中或其上形成一对重掺杂的p（p +）型扩散层，其浓度为5×1019原子/ cm3以上且小于等于1× 1021原子/ cm3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p +型层。

公开(公告)号：US07642165B2

公开(公告)日：2010-01-05

申请号：US11892940

申请日：2007-08-28

申请人： Masao Shingu ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya

发明人： Masao Shingu ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya

IPC分类号： H01L21/8234

CPC分类号： H01L21/28079 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/1203 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/7851

摘要： A semiconductor device having a field effect transistor (FET) with enhanced performance by reduction of electrical contact resistance of electrodes and resistance of the electrodes per se is disclosed. The FET includes an n-type FET having a channel region formed in a semiconductor substrate, a gate electrode insulatively overlying the channel region, and a pair of source and drain electrodes which are formed at both ends of the channel region. The source/drain electrodes are made of silicide of a first metal. An interface layer that contains a second metal is formed in the interface between the substrate and the first metal. The second metal is smaller in work function than silicide of the first metal, and the second metal silicide is less in work function than the first metal silicide. A fabrication method of the semiconductor device is also disclosed.

摘要翻译： 公开了具有通过降低电极的电接触电阻和电极本身的电阻而具有增强的性能的场效应晶体管（FET）的半导体器件。 FET包括具有形成在半导体衬底中的沟道区域，绝缘地覆盖沟道区域的栅极电极和形成在沟道区域两端的一对源极和漏极电极的n型FET。 源极/漏极由第一金属的硅化物制成。 在基板和第一金属之间的界面中形成包含第二金属的界面层。 第二金属的功函数比第一金属的硅化物小，第二金属硅化物的功函数小于第一金属硅化物。 还公开了半导体器件的制造方法。

公开(公告)号：US20090152652A1

公开(公告)日：2009-06-18

申请号：US12323770

申请日：2008-11-26

申请人： Yoshifumi NISHI ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

发明人： Yoshifumi NISHI ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4975 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

公开(公告)号：US07514753B2

公开(公告)日：2009-04-07

申请号：US11761288

申请日：2007-06-11

申请人： Yoshinori Tsuchiya ,  Toshifumi Irisawa ,  Atsuhiro Kinoshita ,  Junji Koga

发明人： Yoshinori Tsuchiya ,  Toshifumi Irisawa ,  Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L29/76

CPC分类号： H01L29/4908 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/785

摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1-a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1-c Gec (0≦c≦1, a≠c).

摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV族元素Si1-a Gea（0≤...） a <= 1），所述p型器件包括形成在所述衬底上的p沟道区，形成在所述p沟道区之间的彼此相对形成的p型源极和漏极区，形成在所述p上的第二栅极绝缘体 以及形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si1-c Gec（0≤c≤1，a≤c）的化合物。

公开(公告)号：US20090008726A1

公开(公告)日：2009-01-08

申请号：US12051947

申请日：2008-03-20

申请人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato

发明人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato

IPC分类号： H01L47/00 ,  H01L21/425

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/785

摘要： A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.

摘要翻译： 提供了制造半导体器件降低n型和p型MISFET的界面电阻的方法。 根据该方法，在第一半导体区域上形成栅极电介质膜和n型MISFET的栅电极，在第二半导体区域上形成p型MISFET的栅极电介质膜和栅电极， 通过将As离子注入第一半导体区域形成n型扩散层，在n型扩散层上沉积含有Ni的第一金属之后，通过第一热处理形成第一硅化物层，制作第一硅化物层 在第一硅化物层和第二半导体区域上沉积含有Ni的第二金属沉积第二热处理之后，在形成第二硅化物层和在第二硅化物层中离子注入B或Mg之后提供第三热处理。

公开(公告)号：US20080308877A1

公开(公告)日：2008-12-18

申请号：US12193668

申请日：2008-08-18

申请人： Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga

发明人： Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga

IPC分类号： H01L27/08

CPC分类号： H01L21/28105 ,  H01L21/28097 ,  H01L21/32155 ,  H01L21/82385 ,  H01L29/66651 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.

摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体基板上的第一栅极绝缘膜; 形成在所述半导体基板上的第二栅极绝缘膜; 形成在第一栅极绝缘膜上并完全硅化的第一栅电极; 以及形成在所述第二栅极绝缘膜上并完全硅化的第二栅电极，所述第二栅电极的栅极长度或栅极宽度大于所述第一栅电极的栅极长度或栅极宽度，并且所述第二栅电极的厚度小于所述第二栅电极的厚度 的第一栅电极。

公开(公告)号：US20050127451A1

公开(公告)日：2005-06-16

申请号：US10997939

申请日：2004-11-29

申请人： Yoshinori Tsuchiya ,  Toshifumi Irisawa ,  Atsuhiro Kinoshita ,  Junji Koga

发明人： Yoshinori Tsuchiya ,  Toshifumi Irisawa ,  Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/4908 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/785

摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1−a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1−c Gec (0≦c≦1, a≠c).

摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV元素Si 1-a的化合物， （0 <= a <= 1），p型器件包括形成在衬底上的p沟道区域，彼此相对形成的p型源极和漏极区域 在其间插入p沟道区域，形成在p沟道区域上的第二栅极绝缘体和形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si _c）。

公开(公告)号：US20130062623A1

公开(公告)日：2013-03-14

申请号：US13404411

申请日：2012-02-24

申请人： Tatsuo SHIMIZU ,  Yoshinori Tsuchiya ,  Takashi Shinohe

发明人： Tatsuo SHIMIZU ,  Yoshinori Tsuchiya ,  Takashi Shinohe

IPC分类号： H01L29/161 ,  H01L21/22

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/26506 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7813

摘要： Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.

摘要翻译： 公开了一种半导体器件，包括：由导电材料形成的第一电极; 连接到第一电极的含有碳（C）的p型第一碳化硅（SiC）半导体部分和n型第二SiC半导体部分230，使得表面密度分布在第一界面处具有与第一 电极。

公开(公告)号：US08367507B1

公开(公告)日：2013-02-05

申请号：US13404779

申请日：2012-02-24

申请人： Yoshinori Tsuchiya ,  Takashi Shinohe

发明人： Yoshinori Tsuchiya ,  Takashi Shinohe

IPC分类号： H01L21/336

CPC分类号： H01L29/7806 ,  H01L21/0485 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/868 ,  H01L29/872

摘要： A method for manufacturing a semiconductor device according to the present embodiment includes the steps of forming a metallic silicide film on an n-type impurity region and a p-type impurity region made of silicon carbide (SiC), performing ion implantation of phosphorous (P) into the metallic silicide film on the n-type impurity region, performing a first thermal treatment, performing ion implantation of aluminum (Al) into the metallic silicide film on the p-type impurity region, and performing a second thermal treatment at a temperature lower than the first thermal treatment.

摘要翻译： 根据本实施例的半导体器件的制造方法包括以下步骤：在n型杂质区上形成金属硅化物膜和由碳化硅（SiC）制成的p型杂质区，进行磷离子注入（P ）进入n型杂质区域的金属硅化物膜，进行第一热处理，对p型杂质区域的金属硅化物膜进行铝（Al）的离子注入，并进行第二次热处理 低于第一次热处理。

公开(公告)号：US08217440B2

公开(公告)日：2012-07-10

申请号：US12881374

申请日：2010-09-14

申请人： Yoshinori Tsuchiya

发明人： Yoshinori Tsuchiya

IPC分类号： H01L29/94

CPC分类号： H01L29/513 ,  H01L21/28167 ,  H01L21/2822 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/78

摘要： MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.

摘要翻译： 提供了MOSFET和制造MOSFET的方法。 根据一个实施例，半导体器件包括衬底和金属氧化物半导体（MOS）晶体管，其包括形成在衬底上的半导体区域，形成在半导体区域中的源极区域和漏极区域彼此分离， 形成在分离源极区域和漏极区域的半导体区域中的沟道区域，在沟道区域上形成的界面氧化物层（IL），其中至少一个与Si，O或N不同的元素以峰值浓度 大于1×1019个原子/ cm 2，以及形成在界面氧化物层上的高k电介质层，其在与IL相似的深度处具有高k / IL界面。 此外，并入元件的至少一个峰值密度深度基本上位于高k / IL界面的下方。