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公开(公告)号:US11876642B2
公开(公告)日:2024-01-16
申请号:US17495824
申请日:2021-10-07
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor: Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
CPC classification number: H04L12/40182 , G06F12/0246 , H04B7/0456 , H04L12/44 , H04W24/10 , H04W88/06
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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公开(公告)号:US20240014916A1
公开(公告)日:2024-01-11
申请号:US17858236
申请日:2022-07-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Thomas Kernen , Dotan David Levi , Bar Or Shapira , Georgi Mihaylov Chalakov , Aviad Itzhak Raveh
IPC: H04J3/06
CPC classification number: H04J3/0697
Abstract: System, methods, and devices for sharing time information between machines are provided. In one example, a system includes a Precision Time Protocol (PTP) Hardware Clock (PHC) and an application. The application receives time information from the PHC along with contextual metadata associated with the time information, analyzes the contextual metadata associated with the time information, and determines a context in which the PHC is disciplined. The context in which the PHC is disciplined may control a manner in which the application uses the time information.
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公开(公告)号:US20240012773A1
公开(公告)日:2024-01-11
申请号:US17858102
申请日:2022-07-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Daniel Marcovitch , Gil Bloch , Richard Graham , Yossef Itigin , Ortal Ben Moshe , Roman Nudelman
IPC: G06F13/28
CPC classification number: G06F13/28 , G06F2213/28
Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.
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公开(公告)号:US11870590B2
公开(公告)日:2024-01-09
申请号:US17107990
申请日:2020-12-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Idan Burstein , Roee Moyal , Ariel Shahar , Noam Bloch , Ran Koren
IPC: H04L1/18 , H04L1/1829 , G06F15/173
CPC classification number: H04L1/1829 , G06F15/17331
Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.
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公开(公告)号:US20240007548A1
公开(公告)日:2024-01-04
申请号:US17855362
申请日:2022-06-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Aviv Kfir , Ortal Ben Moshe , Barak Gafni
CPC classification number: H04L69/22 , H04L45/50 , H04L12/4633
Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a packet parser and a state machine that includes a NULL header state. The packet parser references the state machine to enter the NULL header state automatically in response to parsing a packet header of a predetermined type and then, while in the NULL header state, analyzes a subsequent set of bytes without advancing a parser pointer.
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公开(公告)号:US20230418746A1
公开(公告)日:2023-12-28
申请号:US17958697
申请日:2022-10-03
Applicant: Mellanox Technologies, Ltd.
Inventor: Omri Kahalon , Avi Urman , Ilan Pardo , Omer Cohen , Sayantan Sur , Barak Biber , Saar Tarnopolsky , Ariel Shahar
IPC: G06F12/0802 , G06F9/48
CPC classification number: G06F12/0802 , G06F9/4881 , G06F2212/60
Abstract: A method includes receiving a network packet into a hardware pipeline of a network device; parsing and retrieving information of the network packet; determining, by the hardware pipeline, a packet-processing action to be performed by matching the information to a data structure of a set of flow data structures; sending, by the hardware pipeline, an action request to a programmable core, the action request being populated with data to trigger the programmable core to execute a hardware thread to perform a job, which is associated with the packet-processing action and that generates contextual data; retrieving the contextual data updated by the programmable core; and integrating the contextual data into performing the packet-processing action.
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公开(公告)号:US20230403234A1
公开(公告)日:2023-12-14
申请号:US17835696
申请日:2022-06-08
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Michael Gandelman Milgrom , Daniel Klein , Eitan Zahavi , Vladimir Koushnir , Lion Levi , Gil Mey-Tal , Aleksandr Minchiu
IPC: H04L47/122 , H04L45/02 , H04L45/00
CPC classification number: H04L47/122 , H04L45/02 , H04L45/22
Abstract: An apparatus, system, and method include, for each of two or more switches of a communication network, identifying a set of routing paths from the switch to a destination node based on a topology associated with the communication network. The set of routing paths include a first subset of routing paths and a second subset of routing paths. The topology includes an indication of a convergence of the first subset of routing paths at a node between the switch and the destination node. The apparatus, system, and method include allocating a data flow to a first routing path of the first subset of routing paths and a second routing path of the second subset of routing paths according to a target data flow rate common to the first routing path and the second routing path.
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公开(公告)号:US20230376314A1
公开(公告)日:2023-11-23
申请号:US17748066
申请日:2022-05-19
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Alon Singer , Zachy Haramaty
CPC classification number: G06F9/3836 , G06F9/30145 , G06F9/30101 , G06F9/30189
Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.
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公开(公告)号:US11817906B1
公开(公告)日:2023-11-14
申请号:US17846151
申请日:2022-06-22
Applicant: Mellanox Technologies, Ltd.
Inventor: Mir Ashkan Seyedi , Liron Gantz
IPC: H04B10/40 , H04B10/079 , H04B10/2513 , H04B10/27 , H04B10/2575
CPC classification number: H04B10/40 , H04B10/07951 , H04B10/25133 , H04B10/25759 , H04B10/271
Abstract: A system can include an optical receiver. The optical receiver can have an optical delay component and at least one electrical component (e.g., diode, resistor and/or transistor) operatively coupled to (e.g., integrated within) the optical delay component. The system can further include a processing device, operatively coupled to a memory, that can tune an amount of optical delay implemented by the optical delay component in a low loss and/or low dispersion manner. For example, the processing device can adjust, based on optical delay tuning data (e.g., built-in self-test (BIST) data), the at least one electrical component to modify at least one property of the at least one optical delay component.
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公开(公告)号:US20230350833A1
公开(公告)日:2023-11-02
申请号:US18346616
申请日:2023-07-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Avraham Ganor
CPC classification number: G06F13/4221 , G06F13/4022 , G06F2213/0024
Abstract: Systems and method are provided. An illustrative system includes a first compute node having a first processing unit, a first compute node port, and a first peripheral component interconnect bus configured to carry data between the first processing unit and the first compute node port. The system may further include a multi-host device having a first multi-host port, where the first multi-host port is configured to connect with the first compute node port via a first peripheral component interconnect cable, a network port, where the network port is configured to receive a network interface of a networking cable, and processing circuitry configured to translate and carry data between the first multi-host port and the network port.
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