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122 条记录 (耗时 0.016 秒)

    Method of producing semiconductor memory device
    102.
    发明授权
    Method of producing semiconductor memory device 失效
    半导体存储器件的制造方法

    公开(公告)号：US5286666A

    公开(公告)日：1994-02-15

    申请号：US843599

    申请日：1992-02-28

    申请人： Hisao Katto ,  Jun Sugiura

    发明人： Hisao Katto ,  Jun Sugiura

    IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L21/76218 ,  H01L21/74 ,  H01L27/10805 ,  H01L27/105 ,  Y10S438/953

    摘要： A heavily-doped semiconductor region and a channel stopper region, which are disposed under a memory cell in a memory cell region, are simultaneously formed after formation of a field insulator film, thereby preventing the channel stopper region from oozing out into the channel region, and thus obtaining a semiconductor memory device which is resistant to .alpha.-rays and therefore free from soft errors caused by .alpha.-rays. Also disclosed is a method of producing said semiconductor memory device.

    摘要翻译： 在形成场绝缘膜之后，同时形成设置在存储单元区域中的存储单元下方的重掺杂半导体区域和沟道截止区域，从而防止沟道阻挡区域渗入沟道区域， 从而获得耐受（α）射线并因此没有由（α）射线引起的软错误的半导体存储器件。 还公开了一种制造所述半导体存储器件的方法。

    Method of manufacturing radiation resistant semiconductor device
    103.
    发明授权
    Method of manufacturing radiation resistant semiconductor device 失效
    制造耐辐射半导体器件的方法

    公开(公告)号：US5284793A

    公开(公告)日：1994-02-08

    申请号：US974662

    申请日：1992-11-12

    申请人： Kaoru Hama

    发明人： Kaoru Hama

    IPC分类号： H01L21/28 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/225

    CPC分类号： H01L21/3115 ,  H01L21/28167 ,  H01L21/76213 ,  H01L21/28211 ,  Y10S438/918 ,  Y10S438/953

    摘要： According to this invention, an oxide film is formed on a semiconductor substrate, a metallic boron film or a film containing at least one selected from the group consisting of boron, phosphorus, and arsenic is deposited on the surface of the resultant structure. At least one selected from the group consisting of boron, phosphorus, and arsenic is doped from the metallic boron film or the film containing at least one selected from the group consisting of boron, phosphorus, and arsenic to the oxide film by diffusion without diffusing into the semiconductor substrate. Thus, a semiconductor device having good radiation resistance can be obtained.

    摘要翻译： 根据本发明，在半导体衬底上形成氧化物膜，在所得结构的表面上沉积含有选自硼，磷和砷中的至少一种的金属硼膜或膜。 从金属硼膜或含有选自硼，磷和砷中的至少一种的膜，通过扩散将氧化膜中的至少一种掺杂到硼，磷和砷中，而不会扩散到 半导体衬底。 因此，可以获得具有良好的耐辐射性的半导体器件。

    Technique for forming high-value inter-nodal coupling resistance for rad-hard applications in a double-poly, salicide process using local interconnect
    105.
    发明授权
    Technique for forming high-value inter-nodal coupling resistance for rad-hard applications in a double-poly, salicide process using local interconnect 失效
    在双层，自对准硅化物工艺中使用局部互连形成高硬度连接电阻的技术

    公开(公告)号：US5135882A

    公开(公告)日：1992-08-04

    申请号：US680224

    申请日：1991-04-04

    申请人： Joseph J. Karniewicz

    发明人： Joseph J. Karniewicz

    IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S438/953

    摘要： A technique for forming high-value, inter-nodal, polysilicon coupling resistors using self-aligned silicidation and local interconnect in a double polysilicon process. In an SRAM memory, the technique may be utilized to interconnect the gates of each CMOS invertor to created radiation-hardened cells. Process flow is conventional through gate formation, with transistor gates being patterned from a first polysilicon (poly-1) layer. The transistors which will form each invertor are constructed on distinct active areas. The gate of each invertor transistor extends beyond an edge of the field oxide region, such that an end portion of each gate is superjacent different portions of a single field oxide region. These gate end portions are separated by an expanse of exposed field oxide. The process then departs from convention with a blanket silicon nitride deposition, followed by blanket deposition of a second polysilicon (poly-2) layer. The poly-2 layer is then doped to a desired resistance, then patterned to create a resistive element for the local interconnect. Each invertor gate is connected to the resistive element during the normal flow of the local interconnect process. Preservation of the high resistance of the resistive element is maintained by means of a silicide-isolation oxide film which is created on all but the ends of the resistive element where interconnection to the invertor gates is made. By decoupling the function of the poly-1 and poly-2 layers, the problem of grain-boundary-assisted diffusion between heavily-doped and lightly-doped regions of a contiguous single-poly strip is eliminated. Hence, standard phosphine doping may be used for the poly-1 layer and blanket doping may be used for the poly-2 layer.

    摘要翻译： 一种用于在双重多晶硅工艺中使用自对准硅化和局部互连形成高价值，节间，多晶硅耦合电阻器的技术。 在SRAM存储器中，该技术可以用于将每个CMOS反相器的栅极互连到创建的辐射硬化单元。 工艺流程通过栅极形成是常规的，其中晶体管栅极从第一多晶硅（poly-1）层图案化。 将形成每个反相器的晶体管构建在不同的有源区域上。 每个反相器晶体管的栅极延伸超过场氧化物区域的边缘，使得每个栅极的端部是单个场氧化物区域的不同部分的上部。 这些栅极端部被暴露的场氧化物的一部分分隔开。 然后，该方法随着氮化硅沉积沉积而脱离惯例，随后沉积第二多晶硅（poly-2）层。 然后将聚-2层掺杂到期望的电阻，然后被图案化以产生用于局部互连的电阻元件。 在本地互连过程的正常流程期间，每个逆变器门连接到电阻元件。 通过硅化物隔离氧化膜来保持电阻元件的高电阻的保持，该氧化膜在形成与反相器栅极的互连的电阻元件的除了端部之外的所有端部上产生。 通过去耦合poly-1和poly-2层的功能，消除了连续单多晶带的重掺杂和轻掺杂区域之间的晶界辅助扩散的问题。 因此，标准的磷化氢掺杂可用于多晶硅层，并且覆盖掺杂可用于聚二层。

    Thin oxide sidewall insulators for silicon-over-insulator transistors
    107.
    发明授权
    Thin oxide sidewall insulators for silicon-over-insulator transistors 失效
    用于硅绝缘体晶体管的薄氧化物侧壁绝缘体

    公开(公告)号：US4956307A

    公开(公告)日：1990-09-11

    申请号：US269803

    申请日：1988-11-10

    申请人： Gordon P. Pollack ,  Mishel Matloubian ,  Ravishankar Sundaresan

    发明人： Gordon P. Pollack ,  Mishel Matloubian ,  Ravishankar Sundaresan

    IPC分类号： G21F1/08 ,  H01L21/321 ,  H01L21/336 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L21/32105 ,  H01L29/4908 ,  Y10S257/906 ,  Y10S438/911 ,  Y10S438/953

    摘要： A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

    摘要翻译： 提供了具有覆盖掩埋氧化物（42）的半导体台面（40）的绝缘体上硅晶体管。 绝缘区域（50）形成在半导体台面（40）的侧面。 在台面绝缘区域（46）之上形成可氧化层（56）。 然后对该可氧化层（56）进行各向异性蚀刻，得到可氧化的侧壁（60）。 可选的脚（70）可以形成在可氧化侧壁（76）的底部边缘处。 然后，这些可氧化的侧壁（76）被氧化，产生纯氧化物侧壁（64）。 然后，在纯氧化物侧壁（64）和栅极氧化物（62）上形成栅极（66）。

    Semiconductor memory device having protection against alpha strike induced errors
    108.
    发明授权
    Semiconductor memory device having protection against alpha strike induced errors 失效
    半导体存储器件具有防α射击引起的误差

    公开(公告)号：US4954455A

    公开(公告)日：1990-09-04

    申请号：US259472

    申请日：1988-10-18

    申请人： Drew Wanderman ,  Matthew Weinberg

    发明人： Drew Wanderman ,  Matthew Weinberg

    IPC分类号： H01L21/74 ,  H01L27/102

    CPC分类号： H01L21/74 ,  H01L27/1025 ,  Y10S438/953

    摘要： The invention comprises an improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the transistors in the memory cell, said buried layer being located sufficiently close to a base layer in only the memory portion of the device to provide a sufficiently high capacitance between said buried layer and said base layer to prevent the occurrence of a soft error caused by an alpha particle striking the structure without interfering with the speed of the device.

    摘要翻译： 本发明包括改进的双极存储器件，其具有增强的防止α粒子影响的保护，所述α粒子包括至少一个存储单元，所述至少一个存储单元具有形成存储器单元中的一个晶体管的集电极的至少一部分的掩埋层，所述掩埋层位于 足够接近仅在设备的存储器部分中的基底层，以在所述掩埋层和所述基底层之间提供足够高的电容，以防止由α粒子撞击结构而引起的软误差的发生而不会干扰 装置。

    Process for making polysilicon field plate with improved suppression of parasitic transistors
    110.
    发明授权
    Process for making polysilicon field plate with improved suppression of parasitic transistors 失效
    制造多晶硅场板的方法，具有改进的寄生晶体管抑制

    公开(公告)号：US4900693A

    公开(公告)日：1990-02-13

    申请号：US135809

    申请日：1987-12-21

    申请人： Robert W. Manning

    发明人： Robert W. Manning

    IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/765 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L21/765 ,  Y10S257/906 ,  Y10S438/953

    摘要： A method of forming silicon integrated circuits offers radiation resistance together with a high degree of planarity, including a thin field oxide together with a set of conductive plates over the field region combine to suppress the formation of parasitic transistors. In one embodiment, a silicon substrate is etched to form trenches and is then covered with a thin barrier layer, (410) of high quality thermal oxide. A polysilicon layer (423) is next conformally deposited and planarized until the barrier layer (410) is exposed, followed by an oxidation step for isolation or gate oxide formation.

    摘要翻译： 形成硅集成电路的方法提供了辐射电阻以及高度平坦度，包括薄场氧化物以及场区域上的一组导电板组合以抑制寄生晶体管的形成。 在一个实施例中，蚀刻硅衬底以形成沟槽，然后用薄的阻挡层（410）覆盖高质量的热氧化物。 接下来，将多晶硅层（423）共形沉积并平坦化，直到暴露阻挡层（410），然后进行用于隔离或栅极氧化物形成的氧化步骤。