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公开(公告)号：US09661434B2
公开(公告)日：2017-05-23
申请号：US15342232
申请日：2016-11-03
IPC: H04R29/00
CPC classification number: H04R3/00 , H03F3/183 , H03F2200/03 , H03G3/348 , H04R29/004 , H04R2420/03 , H04R2420/05
Abstract: A host device for use with a removable peripheral apparatus having a microphone, and to the biasing circuitry for said microphone. The host device may have a device connector for forming a mating connection with a respective peripheral connector. A source of bias is arranged to supply an electrical bias to a device microphone contact of the device connector via a biasing path. A capacitor is connected between a reference voltage node and a capacitor node of the biasing path. A first switch is located between the capacitor node and the device microphone contact. Detection circuitry detects disconnection of the peripheral connector and device connector; and control circuitry controls the switch to disable the biasing path.
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112.发明授权公开(公告)号：US09660632B1
公开(公告)日：2017-05-23
申请号：US14971109
申请日：2015-12-16
Inventor： John L. Melanson , Paul Lesso
IPC: H03K7/08
CPC classification number: H03K3/011 , H03F1/303 , H03F3/2171 , H03K7/08 , H03M1/822
Abstract: Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.
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公开(公告)号：US09654871B2
公开(公告)日：2017-05-16
申请号：US14551832
申请日：2014-11-24
Applicant: Wolfson Microelectronics Ltd.
Inventor： Anthony J. Magrath , Richard Clemow
IPC: G10K11/16 , H04R3/00 , G10K11/178
CPC classification number: G10K11/178 , G10K2210/1081 , G10K2210/3026 , G10K2210/3027 , G10K2210/3028 , G10K2210/3051 , H04R3/002
Abstract: A noise cancellation system, comprising: an input for a digital signal, the digital signal having a first sample rate; a digital filter, connected to the input to receive the digital signal; a decimator, connected to the input to receive the digital signal and to generate a decimated signal at a second sample rate lower than the first sample rate; and a processor. The processor comprises: an emulation of the digital filter, connected to receive the decimated signal and to generate an emulated filter output; and a control circuit, for generating a control signal on the basis of the emulated filter output. The control signal is applied to the digital filter to control a filter characteristic thereof.
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公开(公告)号：US09634566B2
公开(公告)日：2017-04-25
申请号：US14612946
申请日：2015-02-03
Applicant: Cirrus Logic, Inc.
Inventor： Eric J. King , John L. Melanson
CPC classification number: H02M3/1582 , H02M3/1588 , H03F1/0227 , H03F3/181 , H03F3/217
Abstract: A switching power stage for producing an output voltage to a load may include a power converter and a controller. The power converter may include a power inductor and plurality of switches arranged to sequentially operate in a plurality of switch configurations. The controller may be configured to, based at least on an input signal to the switching power stage, determine the differential output voltage to be driven at the load, and based on the differential output voltage to be driven at the load, apply a switch configuration from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to generate the differential output voltage.
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公开(公告)号：US09626981B2
公开(公告)日：2017-04-18
申请号：US14745795
申请日：2015-06-22
Applicant: Cirrus Logic, Inc.
Inventor： Brian Parker Chesney
CPC classification number: G10L19/032 , G10L19/005 , G10L19/04 , G10L25/78 , H03M3/424 , H03M3/428 , H03M3/458 , H03M3/466 , H03M3/468 , H03M5/04
Abstract: A system may include a delta-sigma analog-to-digital converter and a digital compression circuit. The delta-sigma analog-to-digital converter may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, a multi-bit quantizer configured to quantize the intermediate signal into an uncompressed digital output signal, and a feedback digital-to-analog converter having a feedback output configured to generate a feedback output signal responsive to the uncompressed digital output signal in order to combine the input signal and the feedback output signal at the loop filter input. The digital compression circuit may be configured to receive the uncompressed digital output signal and compress the uncompressed digital output signal into a compressed digital output signal having fewer quantization levels than that of the uncompressed digital output signal.
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Patent Agency Ranking
116.发明授权公开(公告)号：US09620101B1
公开(公告)日：2017-04-11
申请号：US14048485
申请日：2013-10-08
Applicant: Cirrus Logic, Inc.
Inventor： Bharath Kumar Thandri , Aniruddha Satoskar , Jeffrey D. Alderson , John L. Melanson
IPC: G10K11/16
CPC classification number: G10K11/178 , G10K11/1785 , G10K2210/3212 , H02M3/07 , H03F1/0222 , H03F1/26 , H03F3/187 , H03F3/72 , H03F2200/507
Abstract: An audio amplifier circuit may include a power amplifier, a charge pump power supply, and a control circuit. The power amplifier may have an audio input for receiving an audio input signal, an audio output for providing the output signal, and a power supply input. The charge pump power supply may provide a power supply voltage to the power supply input. The charge pump power supply may have a select input for selecting an operating mode of the power supply. In a first operating mode, the power supply voltage may equal to a first voltage, and in a second operating mode, the power supply voltage may be substantially equal to a second voltage which is a rational fraction of the first voltage. The control circuit may generate the select input based on a magnitude of anti-noise generated by an adaptive noise cancellation system associated with the audio transducer.
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117.发明授权公开(公告)号：US09609701B2
公开(公告)日：2017-03-28
申请号：US14634716
申请日：2015-02-27
Applicant: Cirrus Logic, Inc.
Inventor： John L. Melanson , Ramin Zanbaghi , Thirumalai Rengachari , Prashanth Drakshapalli , Rahul Singh , Arnab Kumar Dutta
CPC classification number: H05B33/0815 , H02M3/335 , H05B33/0845 , H05B33/0887 , H05B37/02
Abstract: A bipolar junction transistor (BJT) may be used in a power stage DC-to-DC converter, such as a converter in LED-based light bulbs. The power stage may be operated by a controller to maintain a desired current output to the LED load. The controller may operate the power stage by monitoring a start and end of a reverse recovery time of the BJT. Information regarding the start and end of the reverse recovery time may be used in the control of the power stage to improve efficiency of the power stage.
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公开(公告)号：US09607603B1
公开(公告)日：2017-03-28
申请号：US14871688
申请日：2015-09-30
Inventor： Samuel P. Ebenezer
IPC: G10K11/16 , G10K11/175
CPC classification number: G10K11/175 , G10L21/0208 , G10L2021/02166 , H04R1/1083 , H04R3/005 , H04R2410/05 , H04R2499/11 , H04R2499/13
Abstract: An adaptive filter of an adaptive blocking matrix in an adaptive beam former or null former may be modified to track and maintain noise correlation between an input and a reference noise signal to the adaptive noise canceller module. That is, a noise correlation factor may be determined, and that noise correlation factor may be used in an inter-sensor signal model applied when generating the blocking matrix output signal. The output signal may then be further processed within the adaptive beamformer to generate a less-noisy representation of the speech signal received at the microphones. The inter-sensor signal model may be estimated using a gradient decent total least squares (GrTLS) algorithm. Further, spatial pre-whitening may be applied in the adaptive blocking matrix to further improve noise reduction.
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公开(公告)号：US09602939B2
公开(公告)日：2017-03-21
申请号：US15195785
申请日：2016-06-28
Applicant: Cirrus Logic, Inc.
Inventor： Antonio John Miller , Jie Su
Abstract: A speaker impedance may be determined by monitoring a voltage and/or current of the speaker. The calculated impedance may be used to determine whether the mobile device containing the speaker is on- or off-ear. The impedance determination may be assisted by applying a test tone low level signal to the speaker. The test tone may be inaudible to the user, but used to determine an impedance of the speaker at the frequency of the test tone. The impedance at that test tone may be used to determine whether a resonance frequency of the speaker is at a frequency corresponding to an on- or off-ear condition. The measured speaker impedance may be provided as feedback to an adaptive noise cancellation (ANC) algorithm to adjust the output at the speaker. For example, when the mobile device is removed from the user's ear, the ANC algorithm may be disabled.
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120.发明授权公开(公告)号：US09599977B1
公开(公告)日：2017-03-21
申请号：US14198076
申请日：2014-03-05
Applicant: Cirrus Logic, Inc.
Inventor： Jean C. Pina , John L. Melanson , Robert T. Grisamore , Eric J. King , Spencer Isaacson
IPC: G05D3/12 , G05B19/042 , G05B19/05
CPC classification number: G05B19/054 , G05B19/0423 , G05B19/0428
Abstract: A power train may have a power train input and a power train output, wherein the power train is configured to transfer electrical energy from the power train input to a load coupled to the power train output in conformity with one or more power train control signals. A scheduler may be configured to receive events from the power train and, responsive to each particular event, schedule execution of a thread of control instructions responsive to the particular event, wherein the thread is selected from a plurality of threads. A processor may be configured to execute the threads of control instructions scheduled by the scheduler, such that for each particular event the processor generates one or more power train control signals responsive to the particular event within a first switching cycle of receipt of the particular event or within a second switching cycle immediately subsequent to the first switching cycle.
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