公开(公告)号：US20090251235A1

公开(公告)日：2009-10-08

申请号：US12371415

申请日：2009-02-13

Applicant: Didier Belot ,  Alexandre Augusto Shirakawa ,  Eric Kerherve ,  Moustapha El Hassan ,  Yann Deval

Inventor： Didier Belot ,  Alexandre Augusto Shirakawa ,  Eric Kerherve ,  Moustapha El Hassan ,  Yann Deval

IPC: H03H9/02

CPC classification number: H03H9/605 ,  H03H9/542

Abstract: A filtering circuit with BAW type acoustic resonators having at least a first quadripole and a second quadripole connected in cascade, each quadripole having a branch series with a first acoustic resonator of type BAW and a branch parallel with each branch having an acoustic resonator of type BAW, the first acoustic resonator having a frequency of resonance series approximately equal to the frequency of parallel resonance of the second acoustic resonator, the branch parallel of the first quadripole having a first capacitance connected in series with the second resonator and, in parallel with the capacitance, a first switching transistor to short circuit the capacitance.

Abstract translation: 具有至少具有级联连接的第一四极和第二四极的BAW型声谐振器的滤波电路，每个四极具有与BAW类型的第一声谐振器的分支系列和与具有BAW型声谐振器的每个分支并联的分支 所述第一声谐振器具有大致等于所述第二声谐振器的并联谐振频率的共振频率，所述第一四极杆的分支并联具有与所述第二谐振器串联连接的第一电容器，并且与所述电容器 第一个开关晶体管使电容短路。

公开(公告)号：US07594119B2

公开(公告)日：2009-09-22

申请号：US10668795

申请日：2003-09-23

Applicant: Sophie Gabriele ,  William Orlando

Inventor： Sophie Gabriele ,  William Orlando

IPC: H04L9/00

CPC classification number: G06Q20/1235 ,  G06Q20/127 ,  G07F15/12 ,  G07F17/0014

Abstract: A system for detecting the time exceeding conditions of at least one application being executed by a processor, including: an element for storing time conditions, the conditions being sorted by increasing deadline order; a register for storing the condition closest to the current date; and a comparator of the deadline contained in the register with the current date of the system.

Abstract translation: 一种用于检测超过由处理器执行的至少一个应用的条件的时间的系统，包括：用于存储时间条件的元素，所述条件通过增加最终期限顺序排序; 用于存储最接近当前日期的条件的寄存器; 以及与该系统当前日期的登记册内的最后期限比较。

公开(公告)号：US07569889B2

公开(公告)日：2009-08-04

申请号：US11343920

申请日：2006-01-30

Applicant: François Jacquet

Inventor： François Jacquet

IPC: H01L29/76

CPC classification number: G11C11/419 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/002

Abstract: A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

Abstract translation: RAM存储器集成电路，特别是SRAM存储器集成电路，包括通过两个存取晶体管布置在两个位线之间的存储器单元矩阵。 在一种情况下，位线被放电，并且在另一种情况下在读取操作期间保持在高预充电电位。 旨在维持在高预充电电位的矩阵的每列的位线以至少两个部分位线的形式产生。 每列的存储单元以分别交替地连接到一个或另一个部分位线的单元组的形式注入。

公开(公告)号：US07564231B2

公开(公告)日：2009-07-21

申请号：US12026098

申请日：2008-02-05

Applicant: Alexandre Balmefrezol ,  Jean-Luc Patry

Inventor： Alexandre Balmefrezol ,  Jean-Luc Patry

IPC: G05F1/40

CPC classification number: H02M1/38 ,  H03K17/165

Abstract: A switching power supply source including an inductance with first and second terminals; an output node; an NMos transistor, the drain of which is connected to the first terminal; a PMos transistor, the drain of which is connected to the first terminal; a control device generating control signals for NMos and PMos transistors assuring that these transistors are not conducting simultaneously; a capacitor with a third terminal connected to the first terminal and a fourth terminal; a resistance with a fifth terminal connected to the fourth terminal and a sixth terminal; and an NMos transistor the drain of which is connected to the grid of the PMos transistor and the gate of which is connected to the fourth terminal.

Abstract translation: 一种开关电源，包括具有第一和第二端子的电感; 输出节点; NMos晶体管，其漏极连接到第一端子; PMOS晶体管，其漏极连接到第一端子; 产生用于NMos和PMos晶体管的控制信号的控制装置，确保这些晶体管不同时导通; 电容器，其具有连接到所述第一端子的第三端子和第四端子; 具有连接到第四端子的第五端子和第六端子的电阻; 以及NMos晶体管，其漏极连接到PMos晶体管的栅极，栅极连接到第四端子。

公开(公告)号：US07560391B2

公开(公告)日：2009-07-14

申请号：US11318369

申请日：2005-12-23

Applicant: Christine Anceau

Inventor： Christine Anceau

IPC: H01L21/302

CPC classification number: H01L21/30608 ,  H01L21/3065 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/76816 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0805 ,  H01L28/91 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening the first thick layer according to the subsequent processings.

Abstract translation: 一种用于在半导体衬底中形成具有不同目的地的阱和/或沟槽的方法，包括根据沟槽和/或阱的图案至少部分同时蚀刻空腔的步骤; 用至少一个第一非共形厚层封闭空腔的开口，并根据随后的处理选择性地打开第一厚层。

公开(公告)号：US07557650B2

公开(公告)日：2009-07-07

申请号：US11716536

申请日：2007-03-09

Applicant: Olivier Giraud ,  Roger Petigny ,  Philippe Marguery

Inventor： Olivier Giraud ,  Roger Petigny ,  Philippe Marguery

IPC: H03F3/38

CPC classification number: H03K7/08 ,  H03F3/2173

Abstract: A generator capable of supplying one or more output signals with a modulated cyclic ratio includes one or more formatting circuits each processing one input signal and one or more class D amplifiers powered with a power supply voltage and being driven by a corresponding one of the formatting circuits. Each formatting circuit has a counter-reaction loop and uses a reference voltage for which the average value is equal to half the power supply voltage. The corresponding output signal is thus corrected for any variations in the power supply voltage.

Abstract translation: 能够提供具有调制循环比率的一个或多个输出信号的发生器包括一个或多个格式化电路，每个格式化电路处理一个输入信号，以及一个或多个D类放大器，其由电源电压供电，并由对应的一个格式化电路驱动 。 每个格式化电路都具有反作用回路，并使用平均值等于电源电压一半的参考电压。 因此，对于电源电压的任何变化，相应的输出信号被校正。

公开(公告)号：US20090146819A1

公开(公告)日：2009-06-11

申请号：US11918372

申请日：2006-04-18

Applicant: Christophe Mani

Inventor： Christophe Mani

IPC: G08B13/22 ,  H01F5/00 ,  H01Q1/38

CPC classification number: G06K19/07771 ,  G06K19/07749 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The invention concerns an inductive element for forming an electromagnetic transponder antenna, comprising a first group of mutually parallel conductors coplanar in a first plane, a second group of mutually parallel conductors coplanar in a second plane parallel to the first plane, and an insulating material separating the two groups of conductors, one end of each conductor of the first group being connected to one end of a conductor of the second group whereof the other end is connected to one end of another conductor of the first group, the connections between the conductors being conductive via holes in the thickness of the insulating material.

Abstract translation: 本发明涉及用于形成电磁应答器天线的电感元件，包括在第一平面内共面的第一组相互平行的导体，在平行于第一平面的第二平面中共面的第二组相互平行的导体，以及分离 两组导体，第一组的每个导体的一端连接到第二组的导体的一端，另一端连接到第一组的另一导体的一端，导体之间的连接为 绝缘材料厚度的导电通孔。

公开(公告)号：US07545035B2

公开(公告)日：2009-06-09

申请号：US11598545

申请日：2006-11-13

Applicant: Jean-Pierre Schoellkopf

Inventor： Jean-Pierre Schoellkopf

IPC: H01L23/48 ,  H01L23/34

CPC classification number: H01L24/72 ,  H01L25/105 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/14

Abstract: A semiconductor device includes several assembled integrated-circuit chips. A main integrated-circuit chip has at least one cavity in which electrical contacts are provided. A secondary integrated-circuit chip includes an edge which engages in the cavity of the main chip and has electrical contacts. When the secondary integrated-circuit chip is inserted into the cavity, the electrical contacts of the main chip and the electrical contacts of the secondary chip are placed so as to be in contact with one another.

Abstract translation: 半导体器件包括几个组装的集成电路芯片。 主集成电路芯片具有至少一个其中提供电触点的空腔。 二次集成电路芯片包括接合在主芯片的空腔中并具有电触点的边缘。 当二次集成电路芯片插入空腔中时，主芯片的电触点和次级芯片的电触点彼此接触放置。

公开(公告)号：US20090134441A1

公开(公告)日：2009-05-28

申请号：US12365475

申请日：2009-02-04

Applicant: Philippe Candellier ,  Thierry Devoivre ,  Emmanuel Josse ,  Sebastien Lefebvre

Inventor： Philippe Candellier ,  Thierry Devoivre ,  Emmanuel Josse ,  Sebastien Lefebvre

IPC: H01L29/94 ,  H01L21/8242

CPC classification number: H01L27/0207 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11246

Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Abstract translation: 非易失性存储元件包括用于选择元件的晶体管和用于通过电容器的绝缘层的电击穿来记录二进制值的电容器。 修改存储元件的结构，以便允许元件在MOS类型的电子电路内更高程度的集成。 此外，存储元件相对于用于记录二进制值的高电压（VDD）更加鲁棒。 该晶体管包括在衬底中的漏极，该漏极沿朝向该电容器延伸的纵向方向具有电场漂移。 用于漏极的电场漂移区域包括与源极相对的晶体管的栅极下面的第一延伸部分和在电容器的绝缘层下方的第二延伸部分。 用于电场漂移区域的衬底的掺杂限于基本上对应于电容器的栅极和电极之间的距离的区域。

公开(公告)号：US20090128198A1

公开(公告)日：2009-05-21

申请号：US12254617

申请日：2008-10-20

Applicant: Franck Badets ,  Thomas Finateu

Inventor： Franck Badets ,  Thomas Finateu

IPC: H03B21/00

CPC classification number: H03K5/135 ,  H03K5/156

Abstract: A digital frequency synthesizer receiving a first signal corresponding to a periodic sequence of first pulses at a first frequency and providing a second signal corresponding to a periodic sequence of second pulses at a second frequency. The synthesizer includes a first circuit clocked by a third signal corresponding to a sequence of third pulses and obtained from the first signal, the first circuit providing a fourth digital signal which, for any set of third successive pulses, increases (decreases) on each pulse and decreases (increases) at the end of said set; and a second circuit receiving the first and fourth signals and providing, for each first pulse from among some at least of the first pulses, a second pulse which is shifted with respect to the first pulse by a duration which depends on the fourth signal.

Abstract translation: 数字频率合成器，以第一频率接收对应于第一脉冲的周期性序列的第一信号，并提供对应于第二频率的第二脉冲的周期性序列的第二信号。 合成器包括由第三信号对应的第三信号的第一电路，该信号对应于从第一信号获得的第三脉冲序列，第一电路提供第四数字信号，对于任何一组第三连续脉冲，在每个脉冲上增加（减小） 并在所述集合的末尾减小（增加）; 以及第二电路，接收所述第一和第四信号，并且对于所述第一脉冲中的至少一些中的每个第一脉冲提供相对于所述第一脉冲移位了取决于所述第四信号的持续时间的第二脉冲。