公开(公告)号：US10379813B1

公开(公告)日：2019-08-13

申请号：US15213728

申请日：2016-07-19

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin P. Ghanekar ,  Pavan Shridhar Jalwadi

IPC: G06F7/24

Abstract: Embodiments may include receiving an input block of data having one or more rows wherein each row includes one or more elements. Embodiments may further include adjusting the input block of data to generate a two-dimensional sorted block of data and identifying at least one position within the two-dimensional sorted block of data that cannot contain a median value or a desired Nth sorted value. Embodiments may also include sorting the two-dimensional block of data along one or more columns to obtain one or more candidate elements that contain the median value or the desired Nth sorted value. Embodiments may include discarding at least one non-candidate element to generate one or more remaining elements and rearranging the one or more remaining elements such that a number of diagonal elements form a column. Embodiments may also include iteratively repeating some of the above operations until a desired value is identified.

公开(公告)号：US10318693B1

公开(公告)日：2019-06-11

申请号：US15690043

申请日：2017-08-29

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Zhuo Li ,  Charles Jay Alpert ,  William Robert Reece ,  Thomas Andrew Newton

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.

公开(公告)号：US10305498B1

公开(公告)日：2019-05-28

申请号：US16146169

申请日：2018-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Mark A. Summers

IPC: H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/095 ,  H03L7/097 ,  G06F17/50

Abstract: Various embodiments provide for a circuit for measuring a frequency difference, a phase difference, or both of at least two clock signals (e.g., a reference clock signal and a feedback clock signal). In particular, various embodiments described herein may be used in a circuit design to convert an input phase of two clock signals to a frequency difference, which may be outputted in the form of a digital word. Additionally, various embodiments described herein may be used in a circuit design to convert an input phase of two clock signals as phase difference output, which may be outputted in the form of a digital word. Various embodiments can provide the frequency difference, the phase difference, or both in near real-time and with only a small amount of latency.

公开(公告)号：US10303230B1

公开(公告)日：2019-05-28

申请号：US15339279

申请日：2016-10-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi ,  Beshara Elmufdi ,  Hitesh Gannu

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/48 ,  G06F9/30

Abstract: Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.

公开(公告)号：US10285276B1

公开(公告)日：2019-05-07

申请号：US15275230

申请日：2016-09-23

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Kukal ,  Arnold Ginetti ,  Steven R. Durrill ,  Abhay Agarwal ,  Vikas Kohli ,  Tyler Lockman

IPC: G06F11/22 ,  G06F17/50 ,  H05K3/00

Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

公开(公告)号：US10282206B1

公开(公告)日：2019-05-07

申请号：US15596942

申请日：2017-05-16

Applicant: Cadence Design Systems, Inc.

Inventor： Fei Sun ,  Tiansi Hu

IPC: G06F9/30

Abstract: According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on the vector register file. In addition, the upper lanes of the vector register file can be clock gated when the scalar operation performs computations. With this gating, the clocks for the entire upper lanes (including the register file, state, semantic, mux, decoder) can be disabled, which provides power savings.

公开(公告)号：US10261887B1

公开(公告)日：2019-04-16

申请号：US15497255

申请日：2017-04-26

Applicant: Cadence Design Systems, Inc.

Inventor： Yonatan Ashkenazi ,  Nadav Chazan ,  Maayan Ziv

IPC: G06F11/00 ,  G06F11/36

Abstract: A method for assertion debugging may include identifying in signals relating to an execution run of a code a segment of time for which an assertion has failed. The method may also include searching in the signals relating to that execution run, or in signals relating to another execution run of that code, to find one or a plurality of segments of time in which the signals are similar to the signals in the identified segment, for which the assertion was successful.

公开(公告)号：US10235490B1

公开(公告)日：2019-03-19

申请号：US15589731

申请日：2017-05-08

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： David Mallon ,  Gilles S. C. Lamant ,  Kenneth Ferguson ,  Monika Bijoy

IPC: G06F17/50 ,  G06F19/00

Abstract: Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

公开(公告)号：US10234504B1

公开(公告)日：2019-03-19

申请号：US15452526

申请日：2017-03-07

Applicant: Cadence Design Systems, Inc.

Inventor： Subhasish Mukherjee ,  Jagjot Kaur ,  Vivek Chickermane ,  Susan Marie Genova

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.

公开(公告)号：US10210301B2

公开(公告)日：2019-02-19

申请号：US14806462

申请日：2015-07-22

Applicant: Cadence Design Systems, Inc.

Inventor： Ankur Chavhan ,  Devesh Jain ,  Behnam Farhat ,  Andrey Freidlin ,  Sundararajan Shanmugam ,  Susan Zueqing Zhang

IPC: G06F17/50

Abstract: A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.