公开(公告)号：US07400027B2

公开(公告)日：2008-07-15

申请号：US11312744

申请日：2005-12-21

Applicant: Young-Soo Joung ,  Yoon-Dong Park ,  In-Kyeong Yoo ,  Myoung-Jae Lee ,  Sun-Ae Seo ,  Hye-Young Kim ,  Seung-Eon Ahn ,  David Seo

Inventor： Young-Soo Joung ,  Yoon-Dong Park ,  In-Kyeong Yoo ,  Myoung-Jae Lee ,  Sun-Ae Seo ,  Hye-Young Kim ,  Seung-Eon Ahn ,  David Seo

IPC: H01L23/62

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/76 ,  G11C2213/77 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold switching characteristics. The nonvolatile semiconductor memory device may include a lower electrode; a first resistance layer having at least two resistance characteristics formed on the lower electrode, a second resistance layer having threshold switching characteristics formed on the first resistance layer, and an upper electrode formed on the second resistance layer.

Abstract translation: 具有两个或多个电阻器的非易失性存储器件及其形成和使用方法。 具有两个电阻层的非易失性存储器件，更具体地说，涉及使用具有存储器开关特性的电阻层和具有阈值转换特性的电阻层形成和操作的非易失性存储器件。 非易失性半导体存储器件可以包括下电极; 具有形成在所述下电极上的至少两个电阻特性的第一电阻层，形成在所述第一电阻层上的阈值转换特性的第二电阻层和形成在所述第二电阻层上的上电极。

公开(公告)号：US20070207619A1

公开(公告)日：2007-09-06

申请号：US10819143

申请日：2004-04-07

Applicant: In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

Inventor： In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

IPC: H01L21/302 ,  H01L21/461

CPC classification number: B82B3/00 ,  B29C59/022 ,  B29C59/026 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/32139

Abstract: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

Abstract translation: 提供一种制造纳米通道阵列的方法和使用纳米通道阵列制造纳米点的方法。 纳米通道阵列制造方法包括：执行第一阳极氧化以形成具有由铝基板上的多个空腔形成的沟道阵列的第一氧化铝层; 将第一氧化铝层蚀刻到预定深度并在铝基板上形成多个凹部，其中每个凹部对应于第一氧化铝层的每个通道的底部; 以及进行第二阳极氧化以形成具有与所述铝基板上的所述多个凹部对应的多个通道的阵列的第二氧化铝层。 阵列制造方法使得可以使用空腔获得精细排列的空腔并形成纳米级点。

公开(公告)号：US20070200158A1

公开(公告)日：2007-08-30

申请号：US11655193

申请日：2007-01-19

Applicant: Stefanovich Genrikh ,  Choong-rae Cho ,  In-kyeong Yoo ,  Eun-hong Lee ,  Sung-Il Cho ,  Chang-wook Moon

Inventor： Stefanovich Genrikh ,  Choong-rae Cho ,  In-kyeong Yoo ,  Eun-hong Lee ,  Sung-Il Cho ,  Chang-wook Moon

IPC: H01L29/94

CPC classification number: H01L27/115 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Abstract translation: 提供具有至少两个氧化物层的电极结构，其更可靠地在不使用附加装置的情况下切换和操作，以及具有该氧化物层的非易失性存储装置。 电极结构可以包括下电极，形成在下电极上的第一氧化物层，形成在第一氧化物层上的第二氧化物层和形成在第二氧化物层上的上电极，其中第一氧化物层和第二氧化物层中的至少一个 可以由电阻变化材料形成。 第一氧化物层可以由具有可变氧化态的氧化物形成。

公开(公告)号：US20070126043A1

公开(公告)日：2007-06-07

申请号：US11606889

申请日：2006-12-01

Applicant: Chang-wook Moon ,  Sang-mock Lee ,  In-kyeong Yoo ,  Seung-woon Lee ,  El Bourim ,  Eun-hong Lee ,  Choong-rae Cho

Inventor： Chang-wook Moon ,  Sang-mock Lee ,  In-kyeong Yoo ,  Seung-woon Lee ,  El Bourim ,  Eun-hong Lee ,  Choong-rae Cho

IPC: H01L29/94

CPC classification number: H01L27/115 ,  B82Y10/00 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/35 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146

Abstract: A storage node having a metal-insulator-metal structure, a non-volatile memory device including a storage node having a metal-insulator-metal (MIM) structure and a method of operating the same are provided. The memory device may include a switching element and a storage node connected to the switching element. The storage node may include a first metal layer, a first insulating layer and a second metal layer, sequentially stacked, and a nano-structure layer. The storage node may further include a second insulating layer and a third metal layer. The nano-structure layer, which is used as a carbon nano-structure layer, may include at least one fullerene layer.

Abstract translation: 提供一种具有金属 - 绝缘体 - 金属结构的存储节点，包括具有金属 - 绝缘体 - 金属（MIM）结构的存储节点的非易失性存储器件及其操作方法。 存储器件可以包括连接到开关元件的开关元件和存储节点。 存储节点可以包括依次层叠的第一金属层，第一绝缘层和第二金属层，以及纳米结构层。 存储节点还可以包括第二绝缘层和第三金属层。 用作碳纳米结构层的纳米结构层可以包括至少一个富勒烯层。

公开(公告)号：US20070085122A1

公开(公告)日：2007-04-19

申请号：US11485340

申请日：2006-07-13

Applicant: Jae-Woong Hyun ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Choong-Rae Cho ,  Sung-Il Cho

Inventor： Jae-Woong Hyun ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Choong-Rae Cho ,  Sung-Il Cho

IPC: H01L29/94

CPC classification number: H01L27/108 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/146

Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

Abstract translation: 半导体存储器件可以具有较低的漏电流和/或更高的可靠性，例如较长的保留时间和/或更短的刷新时间。 该装置可以包括开关装置和电容器。 开关器件的源极可以连接到金属 - 绝缘体转变膜电阻器的第一端，并且电容器的至少一个电极可以连接到金属 - 绝缘体转变膜电阻器的第二端。 金属 - 绝缘体转变膜电阻器可以根据提供给其第一和第二端的电压在绝缘体和导体之间转变。

公开(公告)号：US07091054B2

公开(公告)日：2006-08-15

申请号：US11057469

申请日：2005-02-15

Applicant: In-kyeong Yoo ,  Chang-wook Moon ,  Soo-hwan Jeong ,  Dong-wook Kim

Inventor： In-kyeong Yoo ,  Chang-wook Moon ,  Soo-hwan Jeong ,  Dong-wook Kim

IPC: H01L21/00

CPC classification number: B82Y10/00 ,  H01J1/312 ,  H01J9/022 ,  H01J9/027 ,  H01J2237/31774 ,  H01J2237/31783

Abstract: An emitter for an electron-beam projection lithography (EPL) system and a manufacturing method therefor are provided. The electron-beam emitter includes a substrate, an insulating layer overlying the substrate, and a gate electrode including a base layer formed on top of the insulating layer to a uniform thickness and an electron-beam blocking layer formed on the base layer in a predetermined pattern. The manufacturing method includes steps of: preparing a substrate; forming an insulating layer on the substrate; forming a base layer of a gate electrode by depositing a conductive metal on the insulating layer to a predetermined thickness; forming an electron-beam blocking layer of the gate electrode by depositing a metal capable of anodizing on the base layer to a predetermined thickness; and patterning the electron-beam blocking layer in a predetermined pattern by anodizing. The emitter provides a uniform electric field within the insulating layer and simplify the manufacturing method therefor.

Abstract translation: 提供了一种用于电子束投影光刻（EPL）系统的发射器及其制造方法。 电子束发射器包括衬底，覆盖衬底的绝缘层，以及包括形成在绝缘层顶部上的基底层至均匀厚度的栅极电极和以预定的方式形成在基底层上的电子束阻挡层 模式。 该制造方法包括以下步骤：制备衬底; 在所述基板上形成绝缘层; 通过在所述绝缘层上沉积导电金属至预定厚度来形成栅电极的基层; 通过在基底层上沉积能够阳极氧化的金属至预定的厚度来形成栅电极的电子束阻挡层; 并通过阳极氧化将预定图案中的电子束阻挡层图案化。 发射极在绝缘层内提供均匀的电场，并简化其制造方法。

公开(公告)号：US20060131554A1

公开(公告)日：2006-06-22

申请号：US11312744

申请日：2005-12-21

Applicant: Young-Soo Joung ,  Yoon-Dong Park ,  In-Kyeong Yoo ,  Myoung-Jae Lee ,  Sun-Ae Seo ,  Hye-Young Kim ,  Seung-Eon Ahn ,  David Seo

Inventor： Young-Soo Joung ,  Yoon-Dong Park ,  In-Kyeong Yoo ,  Myoung-Jae Lee ,  Sun-Ae Seo ,  Hye-Young Kim ,  Seung-Eon Ahn ,  David Seo

IPC: H01L29/02

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/76 ,  G11C2213/77 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold switching characteristics. The nonvolatile semiconductor memory device may include a lower electrode; a first resistance layer having at least two resistance characteristics formed on the lower electrode, a second resistance layer having threshold switching characteristics formed on the first resistance layer, and an upper electrode formed on the second resistance layer.

Abstract translation: 具有两个或多个电阻器的非易失性存储器件及其形成和使用方法。 具有两个电阻层的非易失性存储器件，更具体地说，涉及使用具有存储器开关特性的电阻层和具有阈值转换特性的电阻层形成和操作的非易失性存储器件。 非易失性半导体存储器件可以包括下电极; 具有形成在所述下电极上的至少两个电阻特性的第一电阻层，形成在所述第一电阻层上的阈值转换特性的第二电阻层和形成在所述第二电阻层上的上电极。

公开(公告)号：US20060109704A1

公开(公告)日：2006-05-25

申请号：US11267576

申请日：2005-11-07

Applicant: Sun-Ae Seo ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Myoung-Jae Lee

Inventor： Sun-Ae Seo ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Myoung-Jae Lee

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

Abstract: A nonvolatile memory device and method that uses a resistor having various resistance states. The memory device may include a switching device and a resistor. The resistor may be electrically connected with the switching device and may have one reset resistance state and at least two or more set resistance states.

Abstract translation: 一种使用具有各种电阻状态的电阻器的非易失性存储器件和方法。 存储器件可以包括开关器件和电阻器。 电阻器可以与开关器件电连接，并且可以具有一个复位电阻状态和至少两个或多个设定的电阻状态。

公开(公告)号：US20060098472A1

公开(公告)日：2006-05-11

申请号：US11270459

申请日：2005-11-10

Applicant: Seung-Eon Ahn ,  In-Kyeong Yoo ,  Young-Soo Joung ,  Young-Kwan Cha ,  Myoung-Jae Lee ,  David Seo ,  Sun-Ae Seo

Inventor： Seung-Eon Ahn ,  In-Kyeong Yoo ,  Young-Soo Joung ,  Young-Kwan Cha ,  Myoung-Jae Lee ,  David Seo ,  Sun-Ae Seo

IPC: G11C11/22

CPC classification number: G11C13/0007 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a diode structure disposed on the resistor structure, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory devices as described above.

公开(公告)号：US20050202639A1

公开(公告)日：2005-09-15

申请号：US11071192

申请日：2005-03-04

Applicant: In-kyeong Yoo ,  Soo-hwan Jeong ,  Won-il Ryu

Inventor： In-kyeong Yoo ,  Soo-hwan Jeong ,  Won-il Ryu

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/335 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7883

Abstract: Provided is a method of manufacturing a memory device that comprises a gate including uniformly distributed silicon nano dots. The method includes forming a gate on a substrate, the gate including, stacked in sequence an insulating film, nano dot layers separated by a predetermined lateral distance, and a conductive film pattern, forming a source region and a drain region contacting the gate in the substrate, and forming first and second metal layers on the source region and the drain region, respectively.

Abstract translation: 提供一种制造包括均匀分布的硅纳米点的栅极的存储器件的方法。 该方法包括在衬底上形成栅极，栅极包括依次层叠绝缘膜，以预定横向距离分隔的纳米点层和导电膜图案，形成与栅极接触的源极区域和漏极区域 并且分别在源极区域和漏极区域上形成第一和第二金属层。