公开(公告)号：US20050070286A1

公开(公告)日：2005-03-31

申请号：US10674637

申请日：2003-09-30

Applicant: Nikhil Awasthi ,  Richard Jenner ,  Mark Jones

Inventor： Nikhil Awasthi ,  Richard Jenner ,  Mark Jones

IPC: H04W76/06 ,  H04Q7/20

CPC classification number: H04M3/42 ,  H04W76/19

Abstract: The present invention relates to a system and method of reliably determining that a cellular phone call has been dropped and then automatically reconnect the call. The invention is applicable for use in telephone systems that have off-premises call hunting algorithms and thereby use separate telephony channels for the inbound and outbound legs of a call.

Abstract translation: 本发明涉及可靠地确定蜂窝电话呼叫已被丢弃并且然后自动重新连接呼叫的系统和方法。 本发明适用于具有场外呼叫寻呼算法的电话系统，从而为呼叫的入站和出站分支使用单独的电话信道。

公开(公告)号：USD502461S1

公开(公告)日：2005-03-01

申请号：US29199577

申请日：2004-02-17

Applicant: Mark Jones

Designer： Mark Jones

公开(公告)号：US06813753B2

公开(公告)日：2004-11-02

申请号：US10124021

申请日：2002-04-16

Applicant: Anthony Mark Jones

Inventor： Anthony Mark Jones

IPC: G06F1750

CPC classification number: G06F17/5022

Abstract: The present invention relates to a method for pre-characterizing a timing delay curve of a first current component, wherein the timing delay curve has a first curvilinear region and a second, linear method includes determining a first delay equation representing the first, curvilinear region of the delay curve, determining a second delay equation representing the second, linear region of the delay curve, and determining a corner capacitance representing a transition point from the first, curvilinear region to the second, linear region. The present invention further relates to a method of determining a scaling factor and applying the scaling factor to a pre-characterized base component to characterize the timing delay curve of additional circuit components.

Abstract translation: 本发明涉及用于预先表征第一电路部件的定时延迟曲线的方法，其中定时延迟曲线具有第一曲线区域和第二线性区域。 该方法包括确定表示延迟曲线的第一曲线区域的第一延迟方程，确定表示延迟曲线的第二线性区域的第二延迟方程，以及确定表示来自第一曲线区域的转折点的角电容 到第二个线性区域。 本发明还涉及一种确定缩放因子并将缩放因子应用于预表示的基本分量以表征附加电路部件的定时延迟曲线的方法。

公开(公告)号：US06799246B1

公开(公告)日：2004-09-28

申请号：US08991234

申请日：1997-12-16

Applicant: Adrian P. Wise ,  Kevin Douglas Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter J. Claydon ,  Donald W. Walker Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William Philip Robbins ,  Nicholas Birch ,  David Andrew Barnes

Inventor： Adrian P. Wise ,  Kevin Douglas Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter J. Claydon ,  Donald W. Walker Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William Philip Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC: G06F1208

CPC classification number: H04N21/4307 ,  G06F12/0207 ,  G06F12/04 ,  G06F13/16 ,  G06F13/28 ,  H04N19/13 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91 ,  H04N21/4305 ,  H04N21/44004

Abstract: A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Abstract translation: 用于将总线连接到存储器的存储器接口包括输入，缓冲器，地址输入，发生器和写入器。 输入从总线接收多个数据字。 缓冲器缓冲从总线接收的数据字。 地址输入从与多个数据字相关联的总线地址接收。 发生器在存储器中产生一系列可以写入缓冲数据字的地址。 该地址系列从接收到的地址中导出。 写入器将生成的地址将缓冲的数据字写入存储器。

公开(公告)号：US06637713B1

公开(公告)日：2003-10-28

申请号：US09915250

申请日：2001-07-26

Applicant: Robert Bruce Kleve ,  Mark Jones

Inventor： Robert Bruce Kleve ,  Mark Jones

IPC: F23H1300

CPC classification number: F24B1/193

Abstract: The invention comprises a log supporting apparatus for a fireplace having three supporting legs converging upward at an angle toward one another to form a tripod. The apparatus has an upper and lower bracket fitted within the confines of the legs with the legs at 120 degree intervals about a circle and with the brackets having pins projecting outward into bores in the legs to support the legs and brackets with the legs at their inclined angle. The lower bracket is spaced above the bottom of the legs and acts to support the bottoms of the logs with the upper portions of the logs resting at an inclined angle toward one another against the upper bracket whereby ignitable material may be placed beneath the logs and the logs may be easily burned.

Abstract translation: 本发明包括用于壁炉的对数支撑装置，其具有三个支撑腿，其彼此成角度地向上收敛以形成三脚架。 该装置具有安装在腿部的范围内的上部和下部支架，腿部围绕圆圈以120度的间隔安装，并且支架具有向外突出到腿部的孔中的销以将腿部和支架支撑在其倾斜 角度。 下支架在腿的底部上方间隔开，并且用于支撑原木的底部，其中原木的上部以相对于上托架倾斜的角度彼此相对地搁置，从而可将可燃材料放置在原木下方，并且 原木可能很容易烧毁。

公开(公告)号：US06339696B1

公开(公告)日：2002-01-15

申请号：US09435379

申请日：1999-11-05

Applicant: Lawrence K. Y. Chan ,  Sam C. M. Wong ,  Mark Jones

Inventor： Lawrence K. Y. Chan ,  Sam C. M. Wong ,  Mark Jones

IPC: H04B1500

CPC classification number: H04N5/765 ,  H04B1/16 ,  H04B1/20 ,  H04N5/775 ,  H04N21/41422 ,  H04N21/43637 ,  H04R1/1008 ,  H04R1/1041 ,  H04R5/033 ,  H04R2420/07

Abstract: An in-vehicle audio/video system broadcasts audio programming within the vehicle at low power over a system audio channel that is received by a wireless radio frequency receiver that operates in a restricted range to increase tuning resolution and allow fine tuning of the system audio channel. The receiver includes a frequency range adjuster coupled to the tuner. The range adjuster is operable in first and second modes. The first mode selects the frequency range as a full range, and the second mode selects the frequency range as the restricted range.

Abstract translation: 车载音频/视频系统以低功率在低功率下通过无线射频接收机接收的系统音频信道广播音频节目，该无线射频接收机在受限范围内操作以增加调谐分辨率并允许系统音频信道的微调 。 接收机包括耦合到调谐器的频率范围调节器。 范围调节器可在第一和第二模式下操作。 第一种模式选择频率范围为全范围，第二种模式选择频率范围作为限制范围。

公开(公告)号：US5964261A

公开(公告)日：1999-10-12

申请号：US864209

申请日：1997-05-28

Applicant: Steven Neuenfeldt ,  Joanne Daugird ,  James Brauker ,  Robin Lee Geller ,  Scott Fredericksen ,  Mark Jones ,  Thomas Loudovaris ,  David Maryanov ,  Stephanie Shors

Inventor： Steven Neuenfeldt ,  Joanne Daugird ,  James Brauker ,  Robin Lee Geller ,  Scott Fredericksen ,  Mark Jones ,  Thomas Loudovaris ,  David Maryanov ,  Stephanie Shors

IPC: A61L27/00 ,  A61F2/00 ,  A61F2/02 ,  A61K9/00 ,  A61L27/38 ,  A61M31/00

CPC classification number: A61K9/0024 ,  A61F2/0095 ,  A61L27/36 ,  A61L27/38 ,  A61F2/022

Abstract: An implant assembly and methods for loading implant devices which avoids the accidental deposition of transplanted material or other contaminates on the exterior of the device during transportation, storage, and handling are disclosed. The implant assembly of the invention may be used with a large variety of implant devices for implanting a variety of materials such as cells, tissue or other materials into a host. The implant assembly includes an implant device having an elongated port and a first chamber for holding material for implantation and a container with a second chamber for holding the implant device. The container functions to maintain the sterility and protect the physical integrity of the implant device during loading, storage, cryopreservation and transportation and is removed immediately prior to implantation of the device. The container may optionally include liquid media for cellular growth, maintenance, cryostorage, or transportation purposes.

Abstract translation: 公开了一种用于装载植入装置的植入物组件和方法，其避免了在运输，储存和处理期间移植材料或其它污染物意外沉积在装置的外部。 本发明的植入物组件可以与各种各样的植入装置一起使用，用于将诸如细胞，组织或其他材料的各种材料植入宿主体内。 植入物组件包括具有细长端口的植入装置和用于保持用于植入的材料的第一腔室和具有用于保持植入装置的第二腔室的容器。 容器用于维持无菌性并且在加载，储存，冷冻保存和运输期间保护植入物装置的物理完整性，并且在植入植入装置之前立即移除。 容器可以任选地包括用于细胞生长，维持，低温保存或运输目的的液体介质。

公开(公告)号：US5821885A

公开(公告)日：1998-10-13

申请号：US473813

申请日：1995-06-07

Applicant: Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

Inventor： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC: H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC classification number: H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

公开(公告)号：US5740460A

公开(公告)日：1998-04-14

申请号：US481772

申请日：1995-06-07

Applicant: Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

Inventor： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC: H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52 ,  G06F15/66

CPC classification number: H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract translation: 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。

公开(公告)号：US5724537A

公开(公告)日：1998-03-03

申请号：US812820

申请日：1997-03-06

Applicant: Anthony Mark Jones

Inventor： Anthony Mark Jones

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  H04N7/01 ,  H04N7/26 ,  H04N7/50

CPC classification number: G06F12/0207 ,  G06F12/04 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/28 ,  H04N19/423 ,  H04N19/61 ,  H04N19/13 ,  H04N19/91

Abstract: The invention provides a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The interface utilizes a plurality of swing buffers, and has a control module for coordinating accesses thereto, which is connected to the address generator by a specialized two-wire interface. The address generator and the source of data are clocked asynchronously and at different clock rates.

Abstract translation: 本发明提供了一种用于将总线连接到RAM的RAM接口，其中单独的地址发生器产生RAM接口需要寻址RAM的地址。 该接口使用多个摆动缓冲器，并且具有用于协调其访问的控制模块，其通过专门的双线接口连接到地址发生器。 地址发生器和数据源以异步方式以不同的时钟速率进行计时。