公开(公告)号：US11651801B2

公开(公告)日：2023-05-16

申请号：US17135174

申请日：2020-12-28

Applicant: Rambus Inc.

Inventor： Yohan Frans

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  H01L25/065

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US11646724B2

公开(公告)日：2023-05-09

申请号：US17668584

申请日：2022-02-10

Applicant: Rambus Inc.

Inventor： Charles Walter Boecker ,  Roxanne Vu ,  Eric Douglas Groen

IPC: H03K5/13 ,  H03K3/356 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/13 ,  H03K3/356104 ,  H03K5/135 ,  H03K2005/00019

Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

公开(公告)号：US20230135017A1

公开(公告)日：2023-05-04

申请号：US18074217

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Collins Williams ,  Michael Miller ,  Kenneth Wright

IPC: G06F12/0815 ,  G11C14/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

公开(公告)号：US20230120661A1

公开(公告)日：2023-04-20

申请号：US17965684

申请日：2022-10-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US20230119579A1

公开(公告)日：2023-04-20

申请号：US18082446

申请日：2022-12-15

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US11630607B2

公开(公告)日：2023-04-18

申请号：US17521399

申请日：2021-11-08

Applicant: Rambus Inc.

Inventor： Frederick Ware

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

公开(公告)号：US11626876B2

公开(公告)日：2023-04-11

申请号：US17393844

申请日：2021-08-04

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Dhiraj Kumar

IPC: H03K19/007 ,  H03K19/003

Abstract: Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

公开(公告)号：US20230087576A1

公开(公告)日：2023-03-23

申请号：US17940956

申请日：2022-09-08

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dongyun Lee

IPC: G06F3/06

Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.

公开(公告)号：US20230082649A1

公开(公告)日：2023-03-16

申请号：US17931125

申请日：2022-09-11

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US20230081231A1

公开(公告)日：2023-03-16

申请号：US17893790

申请日：2022-08-23

Applicant: Rambus Inc.

Inventor： Taeksang SONG ,  Steven C. WOO ,  Torsten PARTSCH

IPC: G06F3/06

Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.