公开(公告)号：US07179759B2

公开(公告)日：2007-02-20

申请号：US10955519

申请日：2004-09-30

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76826 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the barrier material is not less than about 0.45. The fabrication method of the barrier layer applies a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr substantially without forming crystalline material therein.

Abstract translation: 公开了阻挡层及其制造。 阻挡层包含选自Ta，W，Ti，Ru，Zr，Hf，V，Nb，Cr和Mo中的至少一种阻挡材料和氧，氮或碳的至少一种成分。 组分与阻隔材料的比例不小于约0.45。 阻挡层的制造方法施加用于形成阻挡层的工作压力，大约0.5mTorr至大约200mTorr，基本上不形成结晶材料。

公开(公告)号：US20060292860A1

公开(公告)日：2006-12-28

申请号：US11463515

申请日：2006-08-09

Applicant: Chung-Shi Liu ,  Shau-Lin Shue

Inventor： Chung-Shi Liu ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

Abstract translation: 与镶嵌在FSG（氟化硅酸盐玻璃）中的铜构成的镶嵌结构相关的常见问题是在结构顶表面附近形成缺陷。 本发明通过在图案化之前放置一层USG（未掺杂的硅酸盐玻璃）以避免这种问题，然后在图案化之前对其进行蚀刻，以形成通孔和（用于双镶嵌结构）沟槽。 用铜填充后，使用CMP对结构进行平面化处理。 USG层既可以防止FSG层中的任何氟达到铜，也可以作为CMP中的终点检测器。 以这种方式，铜 - 氟相互作用产生的缺陷不能形成并且实现精确的平坦化。

公开(公告)号：US20060246727A1

公开(公告)日：2006-11-02

申请号：US11115693

申请日：2005-04-27

Applicant: Ching-Hua Hsieh ,  Chao-Chen Chen ,  Shau-Lin Shue ,  Hun-Jan Tao ,  Mong-Song Liang

Inventor： Ching-Hua Hsieh ,  Chao-Chen Chen ,  Shau-Lin Shue ,  Hun-Jan Tao ,  Mong-Song Liang

IPC: H01L21/311 ,  H01L21/306 ,  C23C16/00

CPC classification number: H01L21/76873 ,  H01L21/02063 ,  H01L21/67207 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76843

Abstract: An integrated apparatus comprises a plasma etching station, a wet cleaning station, a de-gassing station, a thin film deposition station, and a wafer transfer mechanism to automatically index wafers between the stations in a predetermined processing order.

Abstract translation: 集成装置包括等离子体蚀刻站，湿式清洁站，除气站，薄膜沉积站和晶片传送机构，用于以预定的处理顺序自动地在台站之间索引晶片。

公开(公告)号：US20060205235A1

公开(公告)日：2006-09-14

申请号：US11420900

申请日：2006-05-30

Applicant: Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76843 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/31625 ,  H01L23/482 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

Abstract translation: 半导体器件及其制造。 在第一电介质层中形成开口，暴露晶体管的有源区，并且在开口中以厚度小于等于一致地形成原子层沉积（ALD）TaN势垒。 在原子层沉积（ALD）TaN势垒上形成铜层以填充开口。

公开(公告)号：US20060138668A1

公开(公告)日：2006-06-29

申请号：US11023296

申请日：2004-12-27

Applicant: Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/06

CPC classification number: H01L23/53238 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

Abstract translation: 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。 在另一个实施例中，形成单个梯度阻挡层。 在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

公开(公告)号：US20060113675A1

公开(公告)日：2006-06-01

申请号：US11001471

申请日：2004-12-01

Applicant: Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L21/76846 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

Abstract translation: 描述了半导体扩散阻挡层及其制造方法。 阻挡层包括至少一层TaN，TiN，WN，TbN，VN，ZrN，CrN，WC，WN，WCN，NbN，AlN及其组合。 阻挡层还可以包括富金属表面。 实施例优选包括约10至500埃厚的胶层，由Ru，Ta，Ti，W，Co，Ni，Al，Nb，AlCu和富含金属的氮化物组成的胶层及其组合。 胶层厚度与阻挡层厚度的比率优选为约1〜50。其他优选实施方案还包括导体退火步骤。 可以使用PVD，CVD，PECVD，PEALD和/或ALD方法沉积各种层，包括氮化和硅化方法。

公开(公告)号：US07015126B2

公开(公告)日：2006-03-21

申请号：US10859730

申请日：2004-06-03

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L2132/05

CPC classification number: H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

Abstract: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

Abstract translation: 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US20050263891A1

公开(公告)日：2005-12-01

申请号：US11100912

申请日：2005-04-07

Applicant: Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

Inventor： Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76867

Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.

Abstract translation: 提供了一种用于半导体器件的镶嵌结构。 在一个实施例中，镶嵌结构包括在通孔上形成的沟槽，其将沟槽电耦合到下面的导电层，使得沟槽具有变化的宽度。 通孔排列有第一阻挡层。 沿着通孔底部的第一阻挡层被去除，使得形成在下面的导电层中的凹陷。 沿着通孔底部形成的凹槽使得较窄沟槽下面的凹陷大于形成在较宽沟槽下方的凹陷。 在另一个实施例中，然后可以在第一阻挡层上形成第二阻挡层。 在该实施例中，导电层的一部分可插入在第一阻挡层和第二阻挡层之间。

公开(公告)号：US20050110147A1

公开(公告)日：2005-05-26

申请号：US10723509

申请日：2003-11-25

Applicant: Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

Inventor： Ping-Kun Wu ,  Horng-Huei Tseng ,  Chine-Gie Lo ,  Chao-Hsiung Wang ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76807 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.

Abstract translation: 铜填充镶嵌结构及其形成方法，包括提供包括半导体衬底的衬底; 在所述基板上形成绝缘体层; 通过所述绝缘体层的厚度部分形成镶嵌开口; 形成扩散阻挡层以使所述镶嵌开口成线; 形成覆盖所述扩散阻挡层的第一晶种层; 用包含选自氩，氮，氢和NH 3的等离子体源气体的第一处理等离子体原位处理第一籽晶层; 形成覆盖所述第一种子层的第二种子层; 根据电化学电镀（ECP）工艺形成覆盖在第二晶种层上的铜层以填充镶嵌开口; 并且平坦化铜层以形成金属互连结构。

公开(公告)号：US20050029665A1

公开(公告)日：2005-02-10

申请号：US10936922

申请日：2004-09-08

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。