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    Passivation structure for semiconductor devices
    1.
    发明申请
    Passivation structure for semiconductor devices 审中-公开
    半导体器件钝化结构

    公开(公告)号：US20060138668A1

    公开(公告)日：2006-06-29

    申请号：US11023296

    申请日：2004-12-27

    申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/06

    CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

    摘要翻译： 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。 在另一个实施例中，形成单个梯度阻挡层。 在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

    SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME
    6.
    发明申请
    SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
    半导体互连结构及其制造方法

    公开(公告)号：US20090117731A1

    公开(公告)日：2009-05-07

    申请号：US11934005

    申请日：2007-11-01

    申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

    发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

    摘要： A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.

    摘要翻译： 如下制造半导体互连结构。 首先，形成具有第一介电层和第二介质层的基板。 随后，在第二电介质层中形成开口。 在开口中的第二电介质层的表面上依次形成薄金属层和种子层，其中金属层包含至少一种具有第二导体的相分离特性的金属物质。 对基板的晶片进行热处理，通过该热处理，开口底部的金属层中的大部分金属物质扩散到第二导体的顶表面，形成金属基氧化物层。 然后，对晶片进行平面化处理，以便将开口外的第二导体移除。

    Damascene interconnect structure with cap layer
    7.
    发明授权
    Damascene interconnect structure with cap layer 有权
    镶嵌互连结构与盖层

    公开(公告)号：US07259463B2

    公开(公告)日：2007-08-21

    申请号：US11004767

    申请日：2004-12-03

    申请人： Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    发明人： Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

    摘要翻译： 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

    Damascene interconnect structure with cap layer
    9.
    发明申请
    Damascene interconnect structure with cap layer 有权
    镶嵌互连结构与盖层

    公开(公告)号：US20060118962A1

    公开(公告)日：2006-06-08

    申请号：US11004767

    申请日：2004-12-03

    申请人： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    发明人： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

    摘要翻译： 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

    Semiconductor device and fabrication method thereof
    10.
    发明申请
    Semiconductor device and fabrication method thereof 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20070152306A1

    公开(公告)日：2007-07-05

    申请号：US11324334

    申请日：2006-01-04

    申请人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

    发明人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

    IPC分类号： H01L23/58 ,  H01L21/4763

    CPC分类号： H01L21/2885 ,  C23C18/1889 ,  C23C18/1893 ,  C25D5/54 ,  C25D13/04 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877

    摘要： A semiconductor device and fabrication method thereof. The semiconductor device comprises a substrate, an electroactive organic layer with conformal step coverage and uniform thickness, and a metal layer. The substrate is a conductive substrate or a nonconductive substrate with a conductive layer formed thereon. The electroactive organic layer and the metal layer are formed sequentially on the conductive substrate or the conductive layer, wherein the electroactive organic layer comprises metal atoms and serves as a seed layer, resulting in the metal layer formed in-situ.

    摘要翻译： 半导体器件及其制造方法。 半导体器件包括基底，具有适形阶梯覆盖和均匀厚度的电活性有机层和金属层。 衬底是其上形成有导电层的导电衬底或非导电衬底。 所述电活性有机层和所述金属层依次形成在所述导电性基板或所述导电层上，其中所述电活性有机层包含金属原子并且用作种子层，导致所述金属层原位形成。