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    Passivation structure for semiconductor devices
    1.
    发明申请
    Passivation structure for semiconductor devices 审中-公开
    半导体器件钝化结构

    公开(公告)号：US20060138668A1

    公开(公告)日：2006-06-29

    申请号：US11023296

    申请日：2004-12-27

    申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/06

    CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

    摘要翻译： 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。 在另一个实施例中，形成单个梯度阻挡层。 在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

    Damascene interconnect structure with cap layer
    4.
    发明授权
    Damascene interconnect structure with cap layer 有权
    镶嵌互连结构与盖层

    公开(公告)号：US07259463B2

    公开(公告)日：2007-08-21

    申请号：US11004767

    申请日：2004-12-03

    申请人： Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    发明人： Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

    摘要翻译： 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

    Damascene interconnect structure with cap layer
    6.
    发明申请
    Damascene interconnect structure with cap layer 有权
    镶嵌互连结构与盖层

    公开(公告)号：US20060118962A1

    公开(公告)日：2006-06-08

    申请号：US11004767

    申请日：2004-12-03

    申请人： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    发明人： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

    摘要翻译： 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

    Uniform passivation method for conductive features
    7.
    发明申请
    Uniform passivation method for conductive features 有权
    导电特性均匀钝化方法

    公开(公告)号：US20060172529A1

    公开(公告)日：2006-08-03

    申请号：US11047836

    申请日：2005-02-01

    申请人： Chien-Hsueh Shih ,  Hung-Wen Su ,  Minghsing Tsai

    发明人： Chien-Hsueh Shih ,  Hung-Wen Su ,  Minghsing Tsai

    IPC分类号： H01L21/465 ,  H01L23/52

    CPC分类号： H01L21/02074 ,  C11D7/08 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02068 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/7685

    摘要： The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

    摘要翻译： 在导电特征上形成钝化层之前，用处理溶液处理导电特征的顶表面。 处理溶液包括清洗溶液和化学接枝前体。 处理溶液还可以包括流平和润湿剂以改善化学接枝前体的覆盖均匀性。 该方法导致在工件的表面上的导电特征上形成均匀的钝化层。

    Silicide structure for ultra-shallow junction for MOS devices
    8.
    发明授权
    Silicide structure for ultra-shallow junction for MOS devices 有权
    用于MOS器件的超浅结的硅化物结构

    公开(公告)号：US07332435B2

    公开(公告)日：2008-02-19

    申请号：US11072038

    申请日：2005-03-04

    申请人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    发明人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

    摘要翻译： 一种形成半导体器件的方法，包括：在沟道区上形成栅介电层; 在所述栅极电介质层上形成栅电极; 形成与所述栅电极的各个边缘基本对准的源极/漏极区域，其间具有沟道区域; 在源/漏区上形成薄金属层; 在所述薄金属层上形成金属合金层; 并将薄金属层转变成低电阻金属硅化物。

    Novel silicide structure for ultra-shallow junction for MOS devices
    9.
    发明申请
    Novel silicide structure for ultra-shallow junction for MOS devices 有权
    用于MOS器件的超浅结的新型硅化物结构

    公开(公告)号：US20060205214A1

    公开(公告)日：2006-09-14

    申请号：US11072038

    申请日：2005-03-04

    申请人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    发明人： Chien-Hsueh Shih ,  Shih-Wei Chou ,  Hung-Wen Su ,  Minghsing Tsai

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

    摘要翻译： 一种形成半导体器件的方法，包括：在沟道区上形成栅介电层; 在所述栅极电介质层上形成栅电极; 形成与所述栅电极的各个边缘基本对准的源极/漏极区域，其间具有沟道区域; 在源/漏区上形成薄金属层; 在所述薄金属层上形成金属合金层; 并将薄金属层转变成低电阻金属硅化物。

    Uniform passivation method for conductive features
    10.
    发明授权
    Uniform passivation method for conductive features 有权
    导电特性均匀钝化方法

    公开(公告)号：US07413976B2

    公开(公告)日：2008-08-19

    申请号：US11047836

    申请日：2005-02-01

    申请人： Chien-Hsueh Shih ,  Hung-Wen Su ,  Minghsing Tsai

    发明人： Chien-Hsueh Shih ,  Hung-Wen Su ,  Minghsing Tsai

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/02074 ,  C11D7/08 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02068 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/7685

    摘要： The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

    摘要翻译： 在导电特征上形成钝化层之前，用处理溶液处理导电特征的顶表面。 处理溶液包括清洗溶液和化学接枝前体。 处理溶液还可以包括流平和润湿剂以改善化学接枝前体的覆盖均匀性。 该方法导致在工件的表面上的导电特征上形成均匀的钝化层。