公开(公告)号：US20080220604A1

公开(公告)日：2008-09-11

申请号：US12062592

申请日：2008-04-04

申请人： Robert J. Purtell ,  Keith Kwong Hon Wong

发明人： Robert J. Purtell ,  Keith Kwong Hon Wong

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.

摘要翻译： 公开了一种用于调整硅化物应力的结构和方法，特别是用于在n-FET的栅极导体上形成拉伸硅化物区域，以优化n-FET性能。 更具体地，在n-FET结构上形成第一金属层保护盖层 - 第二金属层堆叠。 然而，在沉积第二金属层之前，保护层暴露于空气中。 这种空气破碎步骤改变了保护盖层和第二金属层之间的粘附，从而在硅化物形成期间实现施加在第一金属层上的应力。 结果是对于n-FET性能最佳的更强的硅化物。 此外，该方法允许使用相对较薄的第一金属层 - 保护层 - 第二金属层堆叠形成这种拉伸硅化物区域，特别是相对较薄的第二金属层，以最小化在 栅极导体和侧壁间隔件，以避免硅桥接。

公开(公告)号：US07179760B2

公开(公告)日：2007-02-20

申请号：US10908833

申请日：2005-05-27

申请人： Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

发明人： Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

摘要翻译： 本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。 在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层 ）选择性。

公开(公告)号：US07129169B2

公开(公告)日：2006-10-31

申请号：US10709534

申请日：2004-05-12

申请人： Bradley P. Jones ,  Christian Lavoie ,  Robert J. Purtell ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

发明人： Bradley P. Jones ,  Christian Lavoie ,  Robert J. Purtell ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/44 ,  H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/7833

摘要： A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

摘要翻译： 一种用于形成用于半导体器件的金属硅化物接触的方法包括在衬底上形成难熔金属层，该衬底包括所述衬底的有源区和非有源区，并在难熔金属层上形成覆盖层。 反面拉伸层形成在覆盖层上方，其中相对抗拉层选自材料，使得在相对拉伸层和盖层之间产生相对的方向应力，相对于难熔金属之间产生的方向应力 层和盖层。

公开(公告)号：US06896784B2

公开(公告)日：2005-05-24

申请号：US10868723

申请日：2004-06-15

申请人： Tien-Jen Cheng ,  Todd M. Fowler ,  Ajay P. Giri ,  Anton Nenadic ,  Blessen Samuel ,  Keith Kwong Hon Wong

发明人： Tien-Jen Cheng ,  Todd M. Fowler ,  Ajay P. Giri ,  Anton Nenadic ,  Blessen Samuel ,  Keith Kwong Hon Wong

IPC分类号： C25D7/12 ,  C25D5/00 ,  C25D5/02 ,  C25D17/10 ,  C25D17/12 ,  C25D21/12 ,  H01L21/288 ,  H05K3/24

CPC分类号： H01L21/2885 ,  C25D5/02 ,  C25D17/001 ,  C25D17/007 ,  C25D17/10 ,  C25D17/12 ,  H05K3/241

摘要： A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated. The process further includes impressing a current through the electroplating bath between the substrate and the anode, and between the second cathode and the anode, and electroplating the metallic features of different density onto the substrate.

摘要翻译： 一种用于在基片表面上电镀不同密度的金属特征的方法包括提供具有阳极的电镀浴，将基底浸入与阳极间隔开的电镀浴中，该基底包括阴极。 位于基板和阳极之间并且与基板表面相邻并与基板表面分离的电镀槽中的电镀槽是包括具有不同尺寸的开口的金属丝网筛分部分的第二阴极，其符合要电镀的金属特征。 第二阴极屏蔽部分具有较大尺寸的具有更高密度特征的相邻区域的开口，以进行电镀，并且要电镀较低密度特征的较小尺寸的相邻区域的开口。 该方法进一步包括通过电镀浴在基板和阳极之间以及在第二阴极和阳极之间施加电流，并将不同密度的金属特征电镀到基板上。

公开(公告)号：US06700203B1

公开(公告)日：2004-03-02

申请号：US09686742

申请日：2000-10-11

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L2348

CPC分类号： H01L28/20 ,  H01L27/0688

摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

摘要翻译： 公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。 具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通 以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

公开(公告)号：US09142660B2

公开(公告)日：2015-09-22

申请号：US13611113

申请日：2012-09-12

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

摘要： A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

摘要翻译： 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。

公开(公告)号：US09017486B2

公开(公告)日：2015-04-28

申请号：US12878128

申请日：2010-09-09

申请人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong

发明人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong

IPC分类号： B08B7/00 ,  B08B7/04 ,  C23C16/44 ,  C23C14/34

CPC分类号： B08B7/04 ,  B08B7/0014 ,  C23C14/34 ,  C23C16/4404

摘要： A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber.

公开(公告)号：US08916435B2

公开(公告)日：2014-12-23

申请号：US13228767

申请日：2011-09-09

申请人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

发明人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

IPC分类号： H01L21/8242 ,  H01L27/12 ,  H01L27/108 ,  H01L49/02 ,  H01L21/84 ,  H01L29/94

CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/945

摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

摘要翻译： 提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。 在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。 电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层 金属电极。 存储器件还包括与电容器电连通的传输晶体管。

公开(公告)号：US08916405B2

公开(公告)日：2014-12-23

申请号：US13270362

申请日：2011-10-11

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/00 ,  H01L33/26 ,  H01L33/00

CPC分类号： H01L33/0041 ,  H01L33/26 ,  H01L33/34 ,  H01L33/40 ,  H01L51/0048 ,  H01L51/5203 ,  H01L51/5296

摘要： Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

摘要翻译： 提供了碳基发光二极管（LED）及其制造技术。 一方面，提供一种LED。 LED包括基板; 衬底上的绝缘体层; 嵌入在绝缘体层中的第一底栅极和第二底栅极; 第一底栅极和第二底栅极上的栅极电介质; 在第一底栅极和第二底栅上的栅极电介质上的碳材料，其中碳材料用作LED的沟道区域; 并且金属源极和漏极接触到碳材料。

公开(公告)号：US08866214B2

公开(公告)日：2014-10-21

申请号：US13271812

申请日：2011-10-12

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/78 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

摘要： A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.

摘要翻译： 晶体管结构被形成为包括衬底和覆盖衬底的源极; 排水 以及垂直设置在源极和漏极之间的通道。 通道耦合到栅极导体，该栅极导体通过围绕该沟道的栅极电介质材料层围绕该沟道。 栅极导体由具有围绕通道长度的第一部分的第一功函数的第一导电材料和具有围绕通道长度的第二部分的第二功函数的第二导电材料组成。 还公开了制造晶体管结构的方法。 晶体管结构可以表征为具有非对称栅极的垂直场效应晶体管。