公开(公告)号：US5880508A

公开(公告)日：1999-03-09

申请号：US124409

申请日：1998-07-29

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/223 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/2236 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

Abstract: A transistor formed on a semi-conductor substrate, where the transistor includes a gate dielectric layer formed on the semi-conductor substrate. The gate dielectric layer includes a silicon oxynitride sub-layer formed on the semi-conductor substrate and a dielectric sub-layer having relatively high permitivity to an oxide formed on the silicon oxynitride sub-layer. The transistor also includes a barrier layer formed on the gate dielectric layer and a metal gate is formed on the barrier layer. The gate dielectric layer, the barrier layer and the metal gate combine to form a gate structure. Side walls spacers are formed on side walls of the gate structure, and extended source, drain junctions are formed under the side wall spacers in the semi-conductor substrate and adjacent to the gate structure. The transistor also includes source and drain junctions formed in the gate structure next to the extended source, drain junctions.

Abstract translation: 一种形成在半导体衬底上的晶体管，其中晶体管包括形成在半导体衬底上的栅介电层。 栅介电层包括形成在半导体衬底上的氧氮化硅次层和对形成在氧氮化硅亚层上的氧化物具有相对高的介电性的电介质子层。 晶体管还包括形成在栅介质层上的阻挡层，并且在阻挡层上形成金属栅极。 栅极电介质层，势垒层和金属栅极组合形成栅极结构。 侧壁间隔物形成在栅极结构的侧壁上，并且延伸的源极，漏极结形成在半导体衬底中并与栅极结构相邻的侧壁间隔物下方。 晶体管还包括形成在栅极结构中的源极和漏极结，其邻近扩展源，漏极结。

公开(公告)号：US5877056A

公开(公告)日：1999-03-02

申请号：US4448

申请日：1998-01-08

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/2257 ,  H01L29/41783 ,  H01L29/66537 ,  H01L29/7834 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376

Abstract: Following with the formation of pad insulator layer and a stacked layer stacked, a gate insulator is formed within the defined gate insulator space. A lightly doped region is doped and the stacked layer and the pad insulator layer is removed. A semiconductor layer is formed and a gate space is defined over the gate insulator through a spacer structure. An anti punchthrough region is formed followed by the formation of a first insulator layer. A gate filling is then formed to fill within the gate space. A portion of the first insulator layer is then removed. A step of doping a plurality of junction ions is applied. A second insulator layer is formed and a thermal process is then proceeded. Finally a metalization process is employed on the semiconductor substrate.

Abstract translation: 随着衬垫绝缘体层和层叠层的形成，在限定的栅极绝缘体空间内形成栅极绝缘体。 掺杂轻掺杂区域，去除层叠层和焊盘绝缘体层。 形成半导体层，通过间隔结构在栅极绝缘体上形成栅极空间。 形成防穿透区域，然后形成第一绝缘体层。 然后形成浇口填充物以填充浇口空间。 然后去除第一绝缘体层的一部分。 施加掺杂多个结离子的步骤。 形成第二绝缘体层，然后进行热处理。 最后在半导体衬底上采用金属化工艺。

公开(公告)号：US5856226A

公开(公告)日：1999-01-05

申请号：US994053

申请日：1997-12-19

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66583 ,  H01L21/28052 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/1083

Abstract: An ultra-short channel MOSFET with the self-aligned silicided contact and the extended ultra-shallow source/drain junction is formed. An extremely short gate region can be defined without being limited with the bottleneck of the existed lithography technology. A good quality gate insulator layer forming from the regrowth of an oxynitride film is provided. A self aligned metal silicide process is performed to form the contacts. A disposable spacer structure is used to remove metal residue and thus the possible path for leakage is eliminated. An ultra shallow region is formed employing the metal silicide as a diffusion source. An extented source/drain region is provided.

Abstract translation: 形成了具有自对准硅化物接触和扩展超浅源极/漏极结的超短沟道MOSFET。 可以限定非常短的栅极区域，而不受限于存在的光刻技术的瓶颈。 提供了由氮氧化物膜的再生长形成的优质的栅极绝缘体层。 执行自对准金属硅化物工艺以形成触点。 使用一次性间隔件结构来去除金属残留物，因此消除了可能的泄漏路径。 使用金属硅化物作为扩散源形成超浅区域。 提供了扩展的源极/漏极区域。

公开(公告)号：US5854101A

公开(公告)日：1998-12-29

申请号：US825720

申请日：1997-04-04

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238

CPC classification number: H01L21/823864

Abstract: A CMOS process with inverse-T gate LDD structure uses liquid phase deposition (LPD) processes to achieve a low thermal budget with only six photoresist-masks in a CMOS device. A first photoresist-mask is used to form field oxide regions. A second photoresist-mask is used to implant a P-well. Before the second photoresist-mask is removed, a first LPD oxide layer is used to cover the N-well. The second photoresist-mask is removed, and the first LPD oxide layer is used as a mask for implanting the N-well. The first LPD oxide layer is removed and a polysilicon layer is deposited on the substrate. A third photoresist-mask is used to etch the polysilicon layer to form gate-structures for the NMOS and PMOS devices. A conformal amorphous Si layer is formed on the gate-structures, followed by forming a fourth photoresist-mask over the N-well. A conformal LPD oxide layer is formed on the conformal polysilicon layer over the P-well. N-LDD regions are then implanted. An anisotropic etch is performed to form spacers on the sidewalls of the P-well gate-structure. N.sup.+ S/D regions are then implanted. Then, before the fourth photoresist-mask is removed, another LPD oxide layer is formed over the P-well to serve as a P-well mask. Spacers, P-LDD, P.sup.+ S/D regions, and an inverse-T gate are then similarly formed for the PMOS device. The N-well is covered with another LPD oxide layer, which is then covered with a BPSG layer. Fifth and sixth photoresist-masks are then formed to create contacts from the conductive layer.

Abstract translation: 具有逆T栅极LDD结构的CMOS工艺使用液相沉积（LPD）工艺，以在CMOS器件中仅使用六个光致抗蚀剂掩模来实现低热预算。 使用第一光致抗蚀剂掩模形成场氧化物区域。 使用第二光致抗蚀剂掩模来植入P阱。 在除去第二光致抗蚀剂掩模之前，使用第一LPD氧化物层覆盖N阱。 去除第二光致抗蚀剂掩模，并且将第一LPD氧化物层用作用于植入N阱的掩模。 去除第一LPD氧化物层并在衬底上沉积多晶硅层。 使用第三光致抗蚀剂掩模来蚀刻多晶硅层以形成用于NMOS和PMOS器件的栅极结构。 在栅极结构上形成共形非晶Si层，然后在N阱上形成第四光致抗蚀剂掩模。 在P型阱上的共形多晶硅层上形成保形LPD氧化物层。 然后植入N-LDD区域。 执行各向异性蚀刻以在P阱栅极结构的侧壁上形成间隔物。 然后植入N + S / D区。 然后，在除去第四光致抗蚀剂掩模之前，在P阱上形成另一LPD氧化物层以用作P阱掩模。 然后类似地为PMOS器件形成间隔物，P-LDD，P + S / D区域和逆T栅极。 N阱被另一个LPD氧化物层覆盖，然后用BPSG层覆盖。 然后形成第五和第六光致抗蚀剂掩模以从导电层产生接触。

公开(公告)号：US5773348A

公开(公告)日：1998-06-30

申请号：US859754

申请日：1997-05-21

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66537 ,  H01L29/1083 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/66545

Abstract: A method of fabricating a short-channel MOS device on a substrate is provided. First, stacked pad oxide/nitride layers are formed on the substrate. Then a patterned photoresist film is formed on the planned gate region which covers the gate region and its sidewall spacers. A LPD (Liquid Phase Deposition) oxide is selectively deposited on the pad nitride layer by a liquid phase deposition process, except on the pre-formed photoresist film. After removing the photoresist layer nitride spacers leaning against the LPD oxide layer are formed by lithography and etching. The width of the nitride spacers controls the channel length of the MOS device. After forming a gate structure laterally sandwiched by the nitride spacers on the exposed substrate, a two-stage salicide process, which can form shallow junctions and self-aligned contacts on the source and the drain, is performed to complete the MOS device.

Abstract translation: 提供一种在衬底上制造短沟道MOS器件的方法。 首先，在衬底上形成堆叠的衬垫氧化物/氮化物层。 然后，在覆盖栅极区域及其侧壁间隔物的规划栅极区域上形成图案化的光致抗蚀剂膜。 除了在预先形成的光致抗蚀剂膜之外，通过液相沉积工艺，在衬垫氮化物层上选择性地沉积LPD（液相沉积）氧化物。 在去除光致抗蚀剂层之后，通过光刻和蚀刻形成靠在LPD氧化物层上的氮化物间隔物。 氮化物间隔物的宽度控制MOS器件的沟道长度。 在暴露的基板上形成横向被氮化物间隔物夹持的栅极结构之后，进行可在源极和漏极上形成浅结和自对准触点的两级自对准硅化物工艺，以完成MOS器件。

公开(公告)号：US5747377A

公开(公告)日：1998-05-05

申请号：US709169

申请日：1996-09-06

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/311 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76208 ,  H01L21/31144 ,  H01L21/32 ,  Y10S438/947

Abstract: A process for forming a shallow trench isolation is disclosed. Initially, a gate oxide layer is formed on a substrate, and a silicon nitride, which defines an active area, is then patterned on the gate oxide layer. Next, hemispherical grain silicon is formed on the silicon nitride, the sidewalls of the silicon nitride, and the exposed gate oxide layer. Portions of the gate oxide layer are removed to form oxide islands using the silicon nitride and the hemispherical grain silicon as mask. Thereafter, portions of the substrate are removed using the oxide islands as mask. Finally, the exposed substrate is thermally oxidized to form the field oxide structure of the present invention.

Abstract translation: 公开了一种用于形成浅沟槽隔离的工艺。 首先，在衬底上形成栅极氧化层，然后在栅极氧化物层上形成限定有源区的氮化硅。 接下来，在氮化硅，氮化硅的侧壁和暴露的栅极氧化物层上形成半球形晶粒硅。 使用氮化硅和半球形晶粒硅作为掩模去除栅极氧化物层的一部分以形成氧化物岛。 此后，使用氧化物岛作为掩模去除部分基板。 最后，暴露的基底被热氧化以形成本发明的场氧化物结构。

公开(公告)号：US5721168A

公开(公告)日：1998-02-24

申请号：US757102

申请日：1996-12-02

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for forming a ring-shape capacitor in a dynamic random access memory is disclosed. The present invention includes forming a first dielectric layer on a substrate. After a silicon nitride layer is formed on the first dielectric layer, a first doped polysilicon layer is formed on the silicon nitride layer, and a second dielectric layer is formed on the first doped polysilicon layer. After removing portions of the second dielectric layer, the first doped polysilicon layer, the silicon nitride layer and the first dielectric layer by a first photoresist layer, a contact hole is formed. A second doped polysilicon layer is formed over the second dielectric layer, and the contact hole is thus filled by the second doped polysilicon layer. Thereafter, portions of the second doped polysilicon layer and the second dielectric layer are removed using a second photoresist layer as a mask, thereby exposing the first doped polysilicon layer. A third dielectric layer is formed on the second doped polysilicon layer, the first polysilicon layer, and on the sidewalls of the second dielectric layer. After etching back the third dielectric layer, a third doped polysilicon layer is formed. Further etching back the third doped polysilicon to expose the silicon nitride layer and the third dielectric layer, the third dielectric layer, the second dielectric layer, and the silicon nitride layer are removed, thereby forming a ring-shape polysilicon.

Abstract translation: 公开了一种在动态随机存取存储器中形成环形电容器的方法。 本发明包括在基板上形成第一电介质层。 在第一电介质层上形成氮化硅层之后，在氮化硅层上形成第一掺杂多晶硅层，在第一掺杂多晶硅层上形成第二介质层。 在通过第一光致抗蚀剂层去除第二介电层的部分，第一掺杂多晶硅层，氮化硅层和第一介电层之后，形成接触孔。 第二掺杂多晶硅层形成在第二介电层上，因此接触孔由第二掺杂多晶硅层填充。 此后，使用第二光致抗蚀剂层作为掩模去除第二掺杂多晶硅层和第二介电层的部分，从而暴露第一掺杂多晶硅层。 在第二掺杂多晶硅层，第一多晶硅层和第二介电层的侧壁上形成第三电介质层。 在蚀刻回第三电介质层之后，形成第三掺杂多晶硅层。 进一步蚀刻第三掺杂多晶硅以暴露​​氮化硅层和第三介电层，第三介电层，第二介电层和氮化硅层，从而形成环形多晶硅。

公开(公告)号：US20070290234A1

公开(公告)日：2007-12-20

申请号：US11453933

申请日：2006-06-16

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L23/58

CPC classification number: H01L29/872 ,  H01L29/66143 ,  H01L29/8725

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.

Abstract translation: 公开了一种功率肖特基整流器及其制造方法。 肖特基整流器件包括通过在沟槽的侧壁上使用氮化物间隔物作为热氧化掩模在沟槽的底部生长的LOCOS结构。 然后在第一沟槽中填充多晶硅层。 在LOCOS结构下，可选地形成p掺杂区域，以在器件经历反向偏置时使电流泄漏最小化。 通过溅射和退火步骤形成的肖特基势垒硅化物层形成在外延层和多晶硅层的上表面上。 然后在肖特基势垒硅化物层上形成用作阳极的顶部金属层，并延伸以覆盖终止沟槽的一部分场氧化物区域。 然后，在与顶部金属层相对的基板的背面上形成用作阴极电极的金属层。

公开(公告)号：US07064408B2

公开(公告)日：2006-06-20

申请号：US10731503

申请日：2003-12-10

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L29/872

CPC classification number: H01L29/66143 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/872

Abstract: A power Schottky rectifier device having pluralities of trenches are disclosed. The Schottky barrier rectifier device includes field oxide region having p-doped region formed thereunder to avoid premature of breakdown voltage and having a plurality of trenches formed in between field oxide regions to increase the anode area thereto increase forward current capacity or to shrinkage the planar area for driving the same current capacity. Furthermore, the trenches have rounded corners to alleviate current leakage and LOCOS region in the active region to relief stress during the bonding process. The processes for power Schottky barrier rectifier device including termination region formation need only three masks and thus can gain the benefits of cost down.

Abstract translation: 公开了具有多个沟槽的功率肖特基整流器件。 肖特基势垒整流装置包括具有形成在其下面的p掺杂区域的场氧化物区域，以避免击穿电压过早，并且在场氧化物区域之间形成多个沟槽，以增加阳极面积，从而增加正向电流容量或缩小平面面积 用于驱动相同的当前容量。 此外，沟槽具有圆角以减轻有源区域中的电流泄漏和LOCOS区域，以在接合过程中释放应力。 包括终端区域形成的功率肖特基势垒整流器装置的处理只需要三个掩模，从而可以获得降低成本的好处。

公开(公告)号：US20050029614A1

公开(公告)日：2005-02-10

申请号：US10633500

申请日：2003-08-05

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/329 ,  H01L29/872 ,  H01L27/095 ,  H01L29/47 ,  H01L29/861

CPC classification number: H01L29/8725 ,  H01L29/0623 ,  H01L29/66143 ,  H01L29/872

Abstract: A power Schottky rectifier device and its fabrication method are disclosed. The method comprises the following steps: First, a semiconductor substrate having a relatively heavily doped n+ doped layer and a lightly doped is provided. A buried p region is then formed in the epi layer by ion implantation. Afterward, a first oxide layer and a nitride layer are then successively formed on the epi layer. The result structure is then patterned to form trenches. Subsequently, a thermal oxidation step is performed to recover etch damage. A wet etch is then performed to remove the thin oxide layer in the trench to expose the silicon in the sidewall. After that, a silicidation process is then performed to form silicide layer on the n-epi-layer in the trenches. After a removal of un-reacted metal layer, a top metal layer is then formed on the silicide layer and on the first oxide layer or nitride layer. The top metal layer on the termination region portion is then patterned to define anode. Finally, after backside layers formed on the rear surface of the substrate are removed, another cathode layer is formed on the rear surface.

Abstract translation: 公开了一种功率肖特基整流器及其制造方法。 该方法包括以下步骤：首先，提供具有相对重掺杂的n +掺杂层和轻掺杂的半导体衬底。 然后通过离子注入在外延层中形成掩埋的p区。 之后，在epi层上依次形成第一氧化物层和氮化物层。 然后将结果结构图案化以形成沟槽。 随后，进行热氧化步骤以恢复蚀刻损伤。 然后进行湿蚀刻以去除沟槽中的薄氧化物层以露出侧壁中的硅。 之后，然后进行硅化处理以在沟槽中的n外延层上形成硅化物层。 在去除未反应的金属层之后，在硅化物层和第一氧化物层或氮化物层上形成顶部金属层。 然后将终止区域部分上的顶部金属层图案化以限定阳极。 最后，在衬底的后表面上形成的背面层被去除之后，在后表面上形成另一个阴极层。