公开(公告)号：US08174010B2

公开(公告)日：2012-05-08

申请号：US11949993

申请日：2007-12-04

申请人： Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

发明人： Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

摘要翻译： 一种统一的测试结构，其适用于包括具有第一半链和第二半链的电流路径链的半导体器件的所有级别，其中每个半链包括下金属化段，上金属化段，下金属化层之间的绝缘层 段和上部金属化段，以及连接段。 每个连接段电连接到下部金属化段之一的接触区域和上部金属化段之一的接触区域，从而电连接相应的下部金属化段和相应的上部金属化段，并且第一 半链和第二半链具有不同的配置。

公开(公告)号：US20120061818A1

公开(公告)日：2012-03-15

申请号：US13300913

申请日：2011-11-21

申请人： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

发明人： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.

摘要翻译： 在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。 此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

公开(公告)号：US08080866B2

公开(公告)日：2011-12-20

申请号：US12506536

申请日：2009-07-21

申请人： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

发明人： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.

摘要翻译： 在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。 此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

公开(公告)号：US20100289125A1

公开(公告)日：2010-11-18

申请号：US12769124

申请日：2010-04-28

申请人： Frank Feustel ,  Tobias Letz ,  Axel Preusse

发明人： Frank Feustel ,  Tobias Letz ,  Axel Preusse

IPC分类号： H01L23/48 ,  H01L21/441

CPC分类号： H01L21/76849 ,  H01L21/76867 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy that is locally restricted to the interface. To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment.

摘要翻译： 在复杂的半导体器件中，可以通过形成局部限于界面的铜合金来增强铜金属线在其顶部界面处的电迁移性能。 为此，可以在非掩蔽沉积工艺的基础上提供合适的合金形成物质，例如铝，然后通过非掩模蚀刻工艺除去，其中所得合金的特征可以是 在中间热处理期间调整。

公开(公告)号：US20100052134A1

公开(公告)日：2010-03-04

申请号：US12506536

申请日：2009-07-21

申请人： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

发明人： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

IPC分类号： H01L23/52 ,  H01L21/50 ,  H01L21/58 ,  H01L23/373

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.

摘要翻译： 在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。 此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

公开(公告)号：US20090139543A1

公开(公告)日：2009-06-04

申请号：US12124445

申请日：2008-05-21

申请人： Frank Feustel ,  Tobias Letz ,  Christin Bartsch ,  Andreas Ott

发明人： Frank Feustel ,  Tobias Letz ,  Christin Bartsch ,  Andreas Ott

IPC分类号： B08B3/08

CPC分类号： H01L21/02063 ,  H01L21/02068 ,  H01L21/67051 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76861

摘要： By exposing a wet chemical cleaning solution, such as hydrofluoric acid, to a pressurized inert gas ambient prior to applying the solution to patterned dielectric materials of semiconductor devices, the incorporation of oxygen into the liquid during storage and application may be significantly reduced. For instance, by generating a substantially saturated state in the pressurized inert gas ambient, a substantially oversaturated state may be achieved during the application of the liquid in ambient air, thereby enhancing efficiency of the treatment, for instance, by reducing the amount of material removal of exposed copper surfaces after trench patterning, without requiring sophisticated modifications of process chambers.

摘要翻译： 在将溶液施加到半导体器件的图案化电介质材料之前，通过将诸如氢氟酸的湿化学清洁溶液暴露于加压惰性气体环境中，可以显着减少在存储和施加期间将氧气引入液体中。 例如，通过在加压惰性气体环境中产生基本上饱和的状态，在将液体施加到环境空气中时可以实现基本上过饱和的状态，从而提高处理效率，例如通过减少材料去除量 在沟槽图案化之后的暴露的铜表面，而不需要对处理室进行复杂的修改。

公开(公告)号：US20080265247A1

公开(公告)日：2008-10-30

申请号：US11949993

申请日：2007-12-04

申请人： Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

发明人： Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

摘要翻译： 一种统一的测试结构，其适用于包括具有第一半链和第二半链的电流路径链的半导体器件的所有级别，其中每个半链包括下金属化段，上金属化段，下金属化层之间的绝缘层 段和上部金属化段，以及连接段。 每个连接段电连接到下部金属化段之一的接触区域和上部金属化段之一的接触区域，从而电连接相应的下部金属化段和相应的上部金属化段，并且第一 半链和第二半链具有不同的配置。

公开(公告)号：US20060267207A1

公开(公告)日：2006-11-30

申请号：US11347053

申请日：2006-02-03

申请人： Frank Feustel ,  Frank Koschinsky ,  Peter Huebler

发明人： Frank Feustel ,  Frank Koschinsky ,  Peter Huebler

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/32131 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76805 ,  H01L21/76847 ,  H01L21/76873

摘要： In a method of forming a semiconductor structure, an opening is formed in a layer of a dielectric material provided over an electrically conductive feature. An etching process is performed in order to form a recess in the electrically conductive feature. The bottom of the recess may have a rounded shape. The recess and the opening are filled with an electrically conductive material. Due to the provision of the recess, electromigration, stress migration and a local heating of the semiconductor structure, which may adversely affect the functionality of the semiconductor structure, can be reduced.

摘要翻译： 在形成半导体结构的方法中，在设置在导电特征上的介电材料层中形成开口。 执行蚀刻处理以在导电特征中形成凹部。 凹部的底部可以具有圆形形状。 凹部和开口填充有导电材料。 由于设置凹部，可以减少可能不利地影响半导体结构的功能的电迁移，应力迁移和半导体结构的局部加热。

公开(公告)号：US20060267201A1

公开(公告)日：2006-11-30

申请号：US11295756

申请日：2005-12-07

申请人： Peter Huebler ,  Frank Koschinsky ,  Frank Feustel

发明人： Peter Huebler ,  Frank Koschinsky ,  Frank Feustel

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： By providing a stiffening layer at three sidewalls of a trench to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material may be compensated for, at least to a certain degree, thereby reducing electromigration effects and hence increasing lifetime of sophisticated semiconductor devices having metallization layers including low-k dielectric materials in combination with copper-based metal lines.

摘要翻译： 通过在要填充含铜金属的沟槽的三个侧壁处设置加强层，可以至少在一定程度上补偿低k材料的减少的热机械约束，从而降低电迁移效应并因此增加 具有包括低k电介质材料与铜基金属线组合的金属化层的复杂半导体器件的寿命。