公开(公告)号：US20200321393A1

公开(公告)日：2020-10-08

申请号：US16305370

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

公开(公告)号：US20200006630A1

公开(公告)日：2020-01-02

申请号：US16024393

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Gary Allen ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young ,  Ben Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

公开(公告)号：US20190386202A1

公开(公告)日：2019-12-19

申请号：US16012668

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.

公开(公告)号：US20190312086A1

公开(公告)日：2019-10-10

申请号：US16347792

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L27/22 ,  H01L43/10 ,  H01F10/32 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material.

公开(公告)号：US20190305212A1

公开(公告)日：2019-10-03

申请号：US15943461

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Ian Young ,  Dmitri Nikonov ,  Chia-Ching Lin

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.

公开(公告)号：US20190304525A1

公开(公告)日：2019-10-03

申请号：US15943425

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Ian Young

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a magnetization (e.g., a perpendicular magnetization relative to an x-y plane of the apparatus); and an interconnect adjacent to the magnetic junction, wherein the interconnect comprises a chiral antiferromagnetic (AFM) material (e.g., Mn3X, where ‘X’ includes one of: Ge, Sn, Ga, Ir, Rh, or Pt; class-1 kagomi antiferromagnetic material, class-2 hyper kagomi antiferromagnetic material, or metallo-organics).

公开(公告)号：US10347830B2

公开(公告)日：2019-07-09

申请号：US16046189

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: H01L45/00 ,  G06F12/02 ,  G11C14/00 ,  G11C11/16 ,  G11C8/16 ,  G11C11/00 ,  G11C13/00 ,  H01L27/02 ,  H01L27/24

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US20190198754A1

公开(公告)日：2019-06-27

申请号：US16329721

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/10 ,  H01L27/22 ,  H01L41/187 ,  H01L41/193 ,  H01L41/20 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/123 ,  H01F10/126 ,  H01F10/3254 ,  H01L27/228 ,  H01L41/00 ,  H01L41/1871 ,  H01L41/1875 ,  H01L41/1876 ,  H01L41/1878 ,  H01L41/193 ,  H01L41/20 ,  H01L43/02 ,  H01L43/08

Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.

公开(公告)号：US10263036B2

公开(公告)日：2019-04-16

申请号：US15508430

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Asif Khan ,  Raseong Kim ,  Tahir Ghani ,  Ian A. Young

IPC: H01L29/82 ,  H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/20 ,  H01L41/20 ,  H01L43/10 ,  H01L27/11507 ,  H01L27/11502 ,  H01L49/02

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

公开(公告)号：US20190102359A1

公开(公告)日：2019-04-04

申请号：US16147036

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram A. Krishnamurthy ,  Ian A. Young

IPC: G06F17/16 ,  G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G06F9/30 ,  G11C11/56

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.