公开(公告)号：US20150340491A1

公开(公告)日：2015-11-26

申请号：US14814183

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

Abstract translation: 提供了替代金属门（RMG）设备中间隔倒角的方法。 具体地，半导体器件设置有由基板形成的一组翅片; 保形地沉积在该组翅片上的硅基层; 形成在硅基层上的蚀刻停止层（例如，氮化钛（TiN）），该蚀刻停止层对于硅，氧化物和氮化物中的至少一个是选择性的; 一组形成在衬底上的RMG结构; 沿着RMG结构集合中的每一个形成的一组隔离物，其中来自该组间隔物中的每一个的垂直材料层被选择性地移除到蚀刻停止层。 通过倒角每个侧壁间隔件，提供了用于后续功函（WF）金属沉积的较宽区域。 同时，每个晶体管沟道区域被蚀刻停止层（例如，TiN）覆盖，其在反应离子蚀刻期间维持原始栅极临界尺寸。

公开(公告)号：US20150325692A1

公开(公告)日：2015-11-12

申请号：US14270833

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process.

Abstract translation: 公开了在翅片场效应晶体管器件（FinFET）中同时提供一组合并和非鳍片的方法。 在至少一种方法中，FinFET器件包括：一组合并的散热片和一组从衬底形成的未成形翅片，所述一组未合并的散热片邻近该组合的翅片; 以及由该基板形成的平面块，该平面块相邻于一组合并翅片，以及一组未熔合翼片。 FinFET器件还包括在所述一组合并的散热片中的每一个上的外延材料和所述一组未熔合的翅片中的每一个，其中所述外延材料在所述一组合并的翅片上合并在一起，并且保持未被覆盖在所述一组未熔合的翅片上。 在至少一种方法中，使用侧壁图像转印处理形成所述组合的散热片和所述一组未成形散热片。

公开(公告)号：US20150001627A1

公开(公告)日：2015-01-01

申请号：US13929923

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hyun-Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

公开(公告)号：US20200335594A1

公开(公告)日：2020-10-22

申请号：US16386545

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Shesh Mani Pandey

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L21/321

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

公开(公告)号：US20200335435A1

公开(公告)日：2020-10-22

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US20200312947A1

公开(公告)日：2020-10-01

申请号：US16369788

申请日：2019-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L49/02 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768 ,  H01L21/762 ,  H01L23/522

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material

公开(公告)号：US10790363B2

公开(公告)日：2020-09-29

申请号：US16054033

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Kevin J. Ryan ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/66

Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

公开(公告)号：US10756184B2

公开(公告)日：2020-08-25

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Judson R. Holt ,  Steffen A. Sichler ,  Ömür I. Aydin ,  Wei Hong ,  Yi Qi ,  Hui Zang ,  Liu Jiang

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US20200243643A1

公开(公告)日：2020-07-30

申请号：US16256252

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.

公开(公告)号：US10727136B2

公开(公告)日：2020-07-28

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.