公开(公告)号：US11417830B2

公开(公告)日：2022-08-16

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Gary Allen ,  Kaan Oguz ,  Kevin O'Brien ,  Noriyuki Sato ,  Ian Young ,  Dmitri Nikonov

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01L43/10

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US11374164B2

公开(公告)日：2022-06-28

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Kaan Oguz ,  Christopher Wiegand ,  Angeline Smith ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Ian Young ,  Md Tofizur Rahman

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20220181433A1

公开(公告)日：2022-06-09

申请号：US17116315

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Kaan Oguz ,  I-Cheng Tung ,  Uygar E. Avci ,  Matthew V. Metz ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Arnab Sen Gupta

IPC: H01L49/02

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

公开(公告)号：US20210408227A1

公开(公告)日：2021-12-30

申请号：US16914137

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Shriram Shivaraman ,  Sudarat Lee ,  Tanay Gosavi ,  Chia-Ching Lin ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L29/04 ,  H01L29/267 ,  H01L29/06 ,  H01L29/20 ,  H01L21/02 ,  H01L27/092

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

公开(公告)号：US11069609B2

公开(公告)日：2021-07-20

申请号：US16647691

申请日：2017-11-03

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Jasmeet S. Chawla ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young ,  Robert L. Bristol

IPC: H01L23/522 ,  H01F10/32 ,  H01L21/768 ,  H01L23/528 ,  H01L27/22 ,  H01L43/02

Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.

公开(公告)号：US11063131B2

公开(公告)日：2021-07-13

申请号：US16440609

申请日：2019-06-13

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC: B81B3/00 ,  H01L21/00 ,  H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US20190385655A1

公开(公告)日：2019-12-19

申请号：US16009107

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Benjamin Buford ,  Kaan Oguz ,  John J. Plombon ,  Ian A. Young

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

公开(公告)号：US10416217B2

公开(公告)日：2019-09-17

申请号：US14749324

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Chia-Ching Lin ,  Yih Wang ,  Ian A. Young

IPC: G01R31/12 ,  G01R29/26 ,  G11C11/16 ,  G11C29/50 ,  G01R31/28

Abstract: Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.