公开(公告)号：US06211034B1

公开(公告)日：2001-04-03

申请号：US09059546

申请日：1998-04-13

申请人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

发明人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/32139 ,  H01L27/1085

摘要： An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.

摘要翻译： 一种粘附硬掩模结构和蚀刻存储器件电容器结构中的底部电极的方法，其在底部电极的蚀刻期间省去了对任何粘附促进剂的需要。 通过使用氮化硅作为硬掩模220，简化了处理，并且可以产生更坚固的电容器结构。 与通过任何方法形成的氧化硅相比，已经显示氮化硅220产生显着增强的与铂210的粘合性。 由于氮化硅220是抗氧化的，所以它有利地抵抗可能在蚀刻化学中使用的任何氧等离子体。 这种蚀刻工艺可以在> = 256Mbit的DRAM中的高k电容器结构的处理期间使用。

公开(公告)号：US5972722A

公开(公告)日：1999-10-26

申请号：US60152

申请日：1998-04-14

申请人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

发明人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/8242 ,  H01G7/06

CPC分类号： H01L27/1085 ,  H01L21/31116 ,  H01L28/55 ,  H01L28/60

摘要： A high-k dielectric capacitor structure and fabrication method that incorporates an adhesion promoting etch stop layer 200 to promote adhesion of the bottom electrode 220 to the interlevel dielectric layer 210 and to provide a well controlled, repeatable and uniform recess prior to the dielectric 230 deposition. By using a sacrificial layer 200, for example silicon nitride (Si3N4), this layer can act as an etch stop during the recess etch to eliminate parasitic capacitance between adjacent capacitor cells A and B and can promote adhesion of the bottom electrode material 220 to the substrate 210.

摘要翻译： 高k电介质电容器结构和制造方法，其包含粘附促进蚀刻停止层200以促进底部电极220粘附到层间电介质层210，并且在电介质230沉积之前提供良好控制的，可重复的和均匀的凹部 。 通过使用牺牲层200（例如氮化硅（Si 3 N 4）），该层可以在凹陷蚀刻期间用作蚀刻停止以消除相邻的电容器电池A和B之间的寄生电容，并且可以促进底部电极材料220与 衬底210。

公开(公告)号：US08753924B2

公开(公告)日：2014-06-17

申请号：US13414902

申请日：2012-03-08

申请人： James Cooper Wainerdi ,  Luigi Colombo ,  John Paul Tellkamp ,  Robert Reid Doering

发明人： James Cooper Wainerdi ,  Luigi Colombo ,  John Paul Tellkamp ,  Robert Reid Doering

IPC分类号： H01L21/00 ,  H01L23/10

CPC分类号： H01L23/373 ,  B82Y10/00 ,  C09J163/00 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/29076 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/331 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83862 ,  H01L2224/83897 ,  H01L2224/83951 ,  H01L2224/83986 ,  H01L2224/858 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2224/85899 ,  H01L2224/9205 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

摘要： An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

摘要翻译： 一种制造方法包括在管芯（110）的第一侧上具有集成电路（105）的半导体管芯（110），在与第一侧相对的管芯（110）的第二侧上的扩散阻挡层（125） 基于所述扩散阻挡层（125）的碳纳米管（112）垫，与所述碳纳米管的所述垫（112）形成整体的芯片附接粘合剂（115）和粘附到所述模具 附着粘合剂和（115）和碳纳米管的垫（112），以经由碳纳米管（112）在管芯（110）和管芯焊盘（120）之间进行至少一些热转移。 还公开了其它制品，集成电路器件，结构以及制造工艺和组装工艺。

公开(公告)号：US20120231590A1

公开(公告)日：2012-09-13

申请号：US13474927

申请日：2012-05-18

申请人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

发明人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/28 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/76819 ,  H01L21/823842

摘要： A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

摘要翻译： 一种设置硅化半导体器件功能的方法及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物层 层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 介电层界面。

公开(公告)号：US08198707B2

公开(公告)日：2012-06-12

申请号：US12357526

申请日：2009-01-22

申请人： Luigi Colombo ,  Sanjay Banerjee ,  Seyoung Kim ,  Emanuel Tutuc

发明人： Luigi Colombo ,  Sanjay Banerjee ,  Seyoung Kim ,  Emanuel Tutuc

IPC分类号： H01L29/00 ,  H01L21/18

CPC分类号： H01L29/1606 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/513

摘要： A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

摘要翻译： 一种用于在石墨烯上形成均匀薄的电介质层的方法和半导体器件。 金属或半导体层沉积在位于介电层表面或基板表面上的石墨烯上。 金属或半导体层可以用作石墨烯的成核层。 可以对金属或半导体层进行氧化处理。 然后可以在金属或半导体层被氧化之后在石墨烯层上形成薄的电介质层。 作为用作栅极电介质的成核层和用于石墨烯的缓冲液的石墨烯上的金属氧化物层的结果，可以在石墨烯上建立均匀的电介质层，而不影响石墨烯的潜在特性。

公开(公告)号：US20120060279A1

公开(公告)日：2012-03-15

申请号：US13264677

申请日：2010-04-21

申请人： Luigi Colombo

发明人： Luigi Colombo

IPC分类号： A47C17/52

CPC分类号： A47C17/52 ,  A47C17/38

摘要： A pull down bed with automatic locking device has a movable framework, which constitutes a mattress frame, and is hinged to a container body, which constitutes a piece of furniture, so as to define a closed position, in which said mattress frame is substantially inside the piece of furniture, and an open position, for use as a bed, in which the mattress frame is in a horizontal position and rests on the ground by means of two feet. The mattress frame is hinged to the piece of furniture at one end and has its feet at the other end. The pull down bed includes a device for locking said mattress frame in the closed or horizontal position, which is actuated by an actuation device, which includes the feet.

摘要翻译： 具有自动锁定装置的下拉床具有可移动的框架，其构成床垫框架，并铰接到构成一件家具的容器主体上，以限定关闭位置，其中所述床垫框架基本上在其内 家具和开放位置，用作床，其中床垫框架处于水平位置，并通过两个脚搁置在地面上。 床垫框架在一端铰接到一件家具，另一端有脚。 下拉床包括用于将所述床垫框架锁定在封闭或水平位置的装置，其由包括脚的致动装置致动。

公开(公告)号：US20110111586A1

公开(公告)日：2011-05-12

申请号：US13004162

申请日：2011-01-11

申请人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

发明人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/3205

CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/76819 ,  H01L21/823842

摘要： A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

摘要翻译： 一种设置完全硅化半导体器件的功能的方法及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物上的多晶硅层 层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 电介质层界面。

公开(公告)号：US20110091647A1

公开(公告)日：2011-04-21

申请号：US12774342

申请日：2010-05-05

申请人： Luigi Colombo ,  Xuesong Li ,  Rodney S. Ruoff

发明人： Luigi Colombo ,  Xuesong Li ,  Rodney S. Ruoff

IPC分类号： C23C16/44 ,  C23C16/26

CPC分类号： C23C16/26 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186

摘要： Processes for synthesizing graphene films. Graphene films may be synthesized by heating a metal or a dielectric on a substrate to a temperature between 400° C. and 1,400° C. The metal or dielectric is exposed to an organic compound thereby growing graphene from the organic compound on the metal or dielectric. The metal or dielectric is later cooled to room temperature. As a result of the above process, standalone graphene films may be synthesized with properties equivalent to exfoliated graphene from natural graphite that is scalable to size far greater than that available on silicon carbide, single crystal silicon substrates or from natural graphite.

摘要翻译： 合成石墨烯薄膜的方法。 石墨烯膜可以通过将基板上的金属或电介质加热到400℃和1400℃之间的温度来合成。将金属或电介质暴露于有机化合物，从而从金属或电介质上的有机化合物生长石墨烯 。 然后将金属或电介质冷却至室温。 作为上述方法的结果，独立的石墨烯膜可以合成具有相当于天然石墨剥离的石墨烯的性质，该石墨烯的尺寸远大于在碳化硅，单晶硅衬底或天然石墨上可获得的尺寸。

公开(公告)号：US20100224851A1

公开(公告)日：2010-09-09

申请号：US12706116

申请日：2010-02-16

申请人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

发明人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

IPC分类号： H01L29/15 ,  C04B35/536 ,  H01L21/20

CPC分类号： H01L21/02612 ,  H01L21/02527

摘要： A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

摘要翻译： 一种使用碳的离子注入合成石墨烯的方法和半导体器件。 使用离子注入将碳注入金属中。 在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。 然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。 然后去除金属层。 或者，将凹陷区域图案化并蚀刻在位于基底上的电介质层中。 金属后来形成在这些凹陷区域。 然后使用离子注入将碳注入到金属中。 然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。

公开(公告)号：US20090298749A1

公开(公告)日：2009-12-03

申请号：US12476785

申请日：2009-06-02

申请人： Martin Stogniew ,  Luigi Colombo ,  Romeo Clabatti

发明人： Martin Stogniew ,  Luigi Colombo ,  Romeo Clabatti

IPC分类号： A61K38/14 ,  A61P31/04

CPC分类号： C07H7/033 ,  A61K31/704 ,  A61K38/00 ,  C07H13/06 ,  C07H15/203 ,  C07K9/008 ,  Y02A50/475 ,  Y02A50/478 ,  Y02A50/479 ,  Y02A50/481 ,  A61K2300/00

摘要： The invention provides methods and compositions for treatment of bacterial infections. The composition may be a combination of factors, which include A0, A1, B1, B2, C0, C1, isoB0, and MAG, in the presence of low level solvent. Methods of the invention include administration of dalbavancin formulations for treatment of a bacterial infection, in particular a Gram-positive bacterial infection of skin and soft tissue. Dosing regimens include multiple dose administration of dalbavancin, which often remains at therapeutic levels in the bloodstream for at least one week, providing prolonged therapeutic action against a bacterial infection. Dosing regimens for renal patients are also included.

摘要翻译： 本发明提供了用于治疗细菌感染的方法和组合物。 该组合物可以是低浓度溶剂存在下的A0，A1，B1，B2，C0，C1，isoBO和MAG等因素的组合。 本发明的方法包括施用达巴万星制剂用于治疗细菌感染，特别是皮肤和软组织的革兰氏阳性细菌感染。 给药方案包括达巴万星的多剂量给药，其通常在血流中保持治疗水平至少一周，为细菌感染提供长时间的治疗作用。 还包括肾脏患者的给药方案。