公开(公告)号：US08753924B2

公开(公告)日：2014-06-17

申请号：US13414902

申请日：2012-03-08

申请人： James Cooper Wainerdi ,  Luigi Colombo ,  John Paul Tellkamp ,  Robert Reid Doering

发明人： James Cooper Wainerdi ,  Luigi Colombo ,  John Paul Tellkamp ,  Robert Reid Doering

IPC分类号： H01L21/00 ,  H01L23/10

CPC分类号： H01L23/373 ,  B82Y10/00 ,  C09J163/00 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/29076 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/331 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83862 ,  H01L2224/83897 ,  H01L2224/83951 ,  H01L2224/83986 ,  H01L2224/858 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2224/85899 ,  H01L2224/9205 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

摘要： An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

摘要翻译： 一种制造方法包括在管芯（110）的第一侧上具有集成电路（105）的半导体管芯（110），在与第一侧相对的管芯（110）的第二侧上的扩散阻挡层（125） 基于所述扩散阻挡层（125）的碳纳米管（112）垫，与所述碳纳米管的所述垫（112）形成整体的芯片附接粘合剂（115）和粘附到所述模具 附着粘合剂和（115）和碳纳米管的垫（112），以经由碳纳米管（112）在管芯（110）和管芯焊盘（120）之间进行至少一些热转移。 还公开了其它制品，集成电路器件，结构以及制造工艺和组装工艺。

公开(公告)号：US20150140806A1

公开(公告)日：2015-05-21

申请号：US14591566

申请日：2015-01-07

申请人： Cree, Inc.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC分类号： H01L21/768 ,  H01L21/3213

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US20080191944A1

公开(公告)日：2008-08-14

申请号：US11885907

申请日：2006-03-08

申请人： Volker Brod

发明人： Volker Brod

IPC分类号： H01L21/50 ,  H01Q1/38

CPC分类号： H05K3/325 ,  H01L23/49811 ,  H01L23/49855 ,  H01L24/05 ,  H01L24/13 ,  H01L24/72 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81897 ,  H01L2224/83897 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01R4/26 ,  H05K2201/10674 ,  H05K2201/209 ,  H01L2224/45099

摘要： The invention relates to a method for establishing an electrical and mechanical connection between chip contact surfaces of an RFID chip and contact surfaces arranged on a strip-like substrate, wherein the chip contact surfaces which have on their surfaces a plurality of thread-like hooks and/or thread-like eyes are hooked together, under the effect of pressure, with the associated contact surfaces which have on their surfaces a plurality of thread-like eyes and/or thread-like hooks. A transponder is shown.

摘要翻译： 本发明涉及一种用于在RFID芯片的芯片接触表面和布置在条状基板上的接触表面之间建立电气和机械连接的方法，其中芯片接触表面在其表面上具有多个线状钩子， /或线状眼睛在压力作用下被钩在一起，与相关联的接触表面在表面上具有多个线状眼睛和/或线状钩。 显示应答器。

公开(公告)号：US20240297133A1

公开(公告)日：2024-09-05

申请号：US18657384

申请日：2024-05-07

申请人： VueReal Inc.

发明人： Gholamreza Chaji ,  Bahareh Sadeghimakki

IPC分类号： H01L23/00 ,  H01L33/62 ,  H03H3/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/03614 ,  H01L2224/0363 ,  H01L2224/03632 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/056 ,  H01L2224/08225 ,  H01L2224/27614 ,  H01L2224/27632 ,  H01L2224/29005 ,  H01L2224/29019 ,  H01L2224/29078 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29355 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/29439 ,  H01L2224/29499 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29639 ,  H01L2224/32227 ,  H01L2224/80805 ,  H01L2224/80897 ,  H01L2224/83193 ,  H01L2224/83897 ,  H03H3/00

摘要： This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

公开(公告)号：US12014999B2

公开(公告)日：2024-06-18

申请号：US17031587

申请日：2020-09-24

申请人： VueReal Inc.

发明人： Gholamreza Chaji ,  Bahareh Sadeghimakki

IPC分类号： H01G11/36 ,  H01L23/00 ,  H01L33/62 ,  H03H3/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/03614 ,  H01L2224/0363 ,  H01L2224/03632 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/056 ,  H01L2224/08225 ,  H01L2224/27614 ,  H01L2224/27632 ,  H01L2224/29005 ,  H01L2224/29019 ,  H01L2224/29078 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29355 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/29439 ,  H01L2224/29499 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29639 ,  H01L2224/32227 ,  H01L2224/80805 ,  H01L2224/80897 ,  H01L2224/83193 ,  H01L2224/83897 ,  H03H3/00 ,  H01L2224/29139 ,  H01L2924/00014 ,  H01L2224/29609 ,  H01L2924/00014 ,  H01L2224/29611 ,  H01L2924/00014 ,  H01L2224/29639 ,  H01L2924/00014 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29355 ,  H01L2924/00014 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2224/29439 ,  H01L2924/00014

摘要： This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

公开(公告)号：US08970010B2

公开(公告)日：2015-03-03

申请号：US13834196

申请日：2013-03-15

申请人： Cree, Inc.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US20140264868A1

公开(公告)日：2014-09-18

申请号：US13834196

申请日：2013-03-15

申请人： CREE, INC.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US20240363486A1

公开(公告)日：2024-10-31

申请号：US18771548

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yuan Sheng Chiu ,  Chih-Kai Cheng ,  Tsung-Shu Lin

IPC分类号： H01L23/40 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/4006 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/94 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/26155 ,  H01L2224/83897

摘要： In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

公开(公告)号：US12080623B2

公开(公告)日：2024-09-03

申请号：US17322191

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yuan Sheng Chiu ,  Chih-Kai Cheng ,  Tsung-Shu Lin

IPC分类号： H01L23/40 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/4006 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/94 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/26155 ,  H01L2224/83897

摘要： In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

公开(公告)号：US09536783B2

公开(公告)日：2017-01-03

申请号：US14591566

申请日：2015-01-07

申请人： Cree, Inc.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz ,  Van Mieczkowski

IPC分类号： H01L21/283 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L21/3213

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。