利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

719 条记录 (耗时 0.098 秒)

    Electron Blocking Layers for Electronic Devices
    112.
    发明申请
    Electron Blocking Layers for Electronic Devices 审中-公开
    电子设备电子阻挡层

    公开(公告)号：US20080150009A1

    公开(公告)日：2008-06-26

    申请号：US11743085

    申请日：2007-05-01

    申请人： Jian Chen

    发明人： Jian Chen

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/513 ,  B82Y10/00 ,  G11C11/5621 ,  G11C16/10 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/517

    摘要： Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

    摘要翻译： 描述诸如非易失性存储器件的电子设备的方法和装置。 存储器件包括多层控制电介质，例如双层或三层。 多层控制电介质包括高k电介质材料的组合，例如氧化铝（Al 2 O 3 O 3），氧化铪（HfO 2 O 3） SUB>）和/或铪铝氧化物的混合膜。 多层控制电介质提供增强的特性，包括增加的电荷保留，增强的存储器编程/擦除窗口，改进的可靠性和稳定性，具有单或多（例如二，三或四位）操作的可行性。

    Method of reading NAND memory to compensate for coupling between storage elements
    113.
    发明授权
    Method of reading NAND memory to compensate for coupling between storage elements 有权
    读取NAND存储器以补偿存储元件之间的耦合的方法

    公开(公告)号：US07372730B2

    公开(公告)日：2008-05-13

    申请号：US10765693

    申请日：2004-01-26

    申请人： Jian Chen

    发明人： Jian Chen

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3422 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/115

    摘要： A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent word line written after the word line; and reading the selected bit in the word line by selectively adjusting at least one read parameter. In one embodiment, the read parameter is the sense voltage. In another embodiment, the read parameter is the pre-charge voltage. In yet another embodiment, both the sense and the pre-charge voltage are adjusted.

    摘要翻译： 一种用于读取排列成列和行的非易失性存储器的方法，其减少相邻的单元耦合，有时称为Yupin效应。 该方法包括以下步骤：选择要在字线中读取的位; 读取字线后面写的相邻字线; 并且通过选择性地调整至少一个读取参数来读取字线中的所选择的位。 在一个实施例中，读取参数是感测电压。 在另一个实施例中，读取参数是预充电电压。 在另一个实施例中，调整感测电压和预充电电压。

    Read operation for non-volatile storage that includes compensation for coupling
    114.
    发明授权
    Read operation for non-volatile storage that includes compensation for coupling 有权
    非易失性存储的读操作，包括耦合补偿

    公开(公告)号：US07301816B2

    公开(公告)日：2007-11-27

    申请号：US11616762

    申请日：2006-12-27

    申请人： Yan Li ,  Jian Chen

    发明人： Yan Li ,  Jian Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

    摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

    摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

    Reverse coupling effect with timing information
    115.
    发明授权
    Reverse coupling effect with timing information 失效
    反向耦合效应与定时信息

    公开(公告)号：US07289348B2

    公开(公告)日：2007-10-30

    申请号：US11272335

    申请日：2005-11-10

    申请人： Jian Chen

    发明人： Jian Chen

    IPC分类号： G11C19/06

    CPC分类号： G11C16/3418 ,  G11C16/3427

    摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell. Techniques for determining whether the neighbor memory cell was programmed before or after the given memory cell are disclosed.

    摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其他相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了补偿该耦合，如果相邻存储器单元在给定存储器单元之后被编程，则给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。 公开了用于确定相邻存储器单元是否在给定存储器单元之前或之后被编程的技术。

    Dropsophila tumor necrosis factor class molecule (“DmTNFv2”)
    116.
    发明授权
    Dropsophila tumor necrosis factor class molecule (“DmTNFv2”) 有权
    谷类肿瘤坏死因子分子（“DmTNFv2”）

    公开(公告)号：US07288632B2

    公开(公告)日：2007-10-30

    申请号：US11142736

    申请日：2005-06-01

    申请人： Pamela M. Carroll ,  Jian Chen ,  Chandra S. Ramanathan ,  Hong Xiao ,  Bo Guan ,  Michael A. Bowen

    发明人： Pamela M. Carroll ,  Jian Chen ,  Chandra S. Ramanathan ,  Hong Xiao ,  Bo Guan ,  Michael A. Bowen

    IPC分类号： C07K14/00

    CPC分类号： C07K14/525 ,  A01K2217/05

    摘要： The present invention provides novel polynucleotides encoding Drosophila DmTNF polypeptides, fragments and homologs thereof. The present invention also is directed to novel polynucleotides encoding two Drosophila DmTNF variants, DmTNFv1 and DmTNFv2 polypeptides, fragments and homologs thereof. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention, in addition to methods of genetically modifying Drosophila or cultured cells to express or mis-express DmTNF, DmTNFv1, or DmTNFv2. The invention also relates to the use of such modified insects or cells to characterize DmTNF activity, identify TNF-like genes and/or genes implicated in modulating TNF, characterize TNF signaling pathways, and/or to identify modulators of DmTNF activity.

    摘要翻译： 本发明提供了编码果蝇DmTNF多肽的新型多核苷酸，其片段和同系物。 本发明还涉及编码两种果蝇DmTNF变体，DmTNFv1和DmTNFv2多肽的新型多核苷酸，其片段和同系物。 还提供了载体，宿主细胞，抗体以及用于产生所述多肽的重组和合成方法。 除了遗传修饰果蝇或培养细胞以表达或错误表达DmTNF，DmTNFv1或DmTNFv2的方法之外，本发明还涉及用于鉴定本发明的多核苷酸和多肽的激动剂和拮抗剂的筛选方法。 本发明还涉及这种修饰的昆虫或细胞用于表征DmTNF活性，鉴定涉及调节TNF，表征TNF信号传导途径和/或鉴定DmTNF活性调节剂的TNF-样基因和/或基因的用途。

    Semiconductor device having trench isolation for differential stress and method therefor
    117.
    发明授权
    Semiconductor device having trench isolation for differential stress and method therefor 有权
    具有用于差分应力的沟槽隔离的半导体器件及其方法

    公开(公告)号：US07288447B2

    公开(公告)日：2007-10-30

    申请号：US10977226

    申请日：2005-01-18

    申请人： Jian Chen ,  Thien T. Nguyen ,  Michael D. Turner ,  James E. Vasek

    发明人： Jian Chen ,  Thien T. Nguyen ,  Michael D. Turner ,  James E. Vasek

    IPC分类号： H01L21/64

    CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7846

    摘要： A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.

    摘要翻译： 半导体器件具有用于定义有源区的沟槽。 在沟槽中沉积薄的扩散屏障之后，选择性地蚀刻一些沟槽以在沟槽中留下不同的区域。 其中一个区域具有完全去除扩散阻挡层，使底层被暴露。 另一个区域仍然存在扩散屏障。 遵循氧化步骤，使得氧化发生在去除扩散阻挡层的拐角处，而氧化被作为氧阻挡的扩散阻挡层阻挡。 用于氧化的角是那些需要压应力的角，例如沿着P沟道晶体管的边界的一部分。 留下扩散阻挡层的角部是不期望压缩应力的角，例如N沟道晶体管的边界。

    Systems for Variable Reading in Non-Volatile Memory
    118.
    发明申请
    Systems for Variable Reading in Non-Volatile Memory 有权
    非易失性存储器中可变读取系统

    公开(公告)号：US20070247916A1

    公开(公告)日：2007-10-25

    申请号：US11770466

    申请日：2007-06-28

    申请人： Jian Chen ,  Chi-Ming Wang

    发明人： Jian Chen ,  Chi-Ming Wang

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

    摘要： Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

    摘要翻译： 根据各种实施例的系统和方法可以提供非易失性半导体存储器中减少的程序干扰。 在一个实施例中，使用与编程其他单元或字线的相应级别不同的一个或多个程序验证电平或电压对连接到NAND串的最后字线的选择存储器单元进行编程。 一个示例性实施例包括在编程在程序操作期间编程用于字符串的最后一个字线时，使用较低的阈值电压验证电平来选择物理状态。 另一个实施例包括将较低编程电压施加到最后字线的编程存储单元以选择物理状态。 在一些示例性实施方式中，建立读取使用较低验证电平编程的状态的附加读取电平。 在一个实施例中，当编程选择存储器单元或字线（诸如要为NAND串编程的最后字线）时，使用大于标称步长的第二编程电压步长。

    Metalloprotease highly expressed in the testis, MMP-29
    119.
    发明授权
    Metalloprotease highly expressed in the testis, MMP-29 有权
    金属蛋白酶在睾丸中高度表达，MMP-29

    公开(公告)号：US07285633B2

    公开(公告)日：2007-10-23

    申请号：US11313356

    申请日：2005-12-21

    申请人： Shujian Wu ,  Jian Chen ,  John N. Feder ,  Liana Lee ,  Stanley R. Krystek

    发明人： Shujian Wu ,  Jian Chen ,  John N. Feder ,  Liana Lee ,  Stanley R. Krystek

    IPC分类号： A61K38/17

    CPC分类号： C12N9/6489

    摘要： The present invention provides novel polynucleotides encoding MMP-29 polypeptides, fragments and homologues thereof. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to diagnostic and therapeutic methods for applying these novel MMP-29 polypeptides to the diagnosis, treatment, and/or prevention of various diseases and/or disorders related to these polypeptides. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention.

    摘要翻译： 本发明提供了编码MMP-29多肽的新型多核苷酸，其片段和同源物。 还提供了载体，宿主细胞，抗体以及用于产生所述多肽的重组和合成方法。 本发明还涉及将这些新型MMP-29多肽应用于诊断，治疗和/或预防与这些多肽相关的各种疾病和/或病症的诊断和治疗方法。 本发明还涉及用于鉴定本发明的多核苷酸和多肽的激动剂和拮抗剂的筛选方法。