公开(公告)号：US20200176063A1

公开(公告)日：2020-06-04

申请号：US16782720

申请日：2020-02-05

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US10529434B2

公开(公告)日：2020-01-07

申请号：US16129497

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Ting Luo ,  Ashutosh Malshe ,  Preston Thomson ,  Jianmin Huang

IPC: G11C7/00 ,  G11C16/34 ,  G06F1/30 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G06F1/16 ,  G11C29/02

Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.

公开(公告)号：US10446237B1

公开(公告)日：2019-10-15

申请号：US16024316

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Jung Sheng Hoei ,  Harish Reddy Singidi ,  Ting Luo ,  Ankit Vashi

IPC: G11C16/10 ,  G11C16/34 ,  G11C7/04

Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

公开(公告)号：US10347344B2

公开(公告)日：2019-07-09

申请号：US15689747

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C11/34 ,  G11C16/06 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20190130981A1

公开(公告)日：2019-05-02

申请号：US16129497

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Ting Luo ,  Ashutosh Malshe ,  Preston Thomson ,  Jianmin Huang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G06F1/16 ,  G06F1/30 ,  G11C29/02

CPC classification number: G11C16/3404 ,  G06F1/1635 ,  G06F1/305 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028

Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.

公开(公告)号：US20190066817A1

公开(公告)日：2019-02-28

申请号：US16129422

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC: G11C29/38 ,  G06F11/07 ,  G11C29/44

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

公开(公告)号：US10121551B1

公开(公告)日：2018-11-06

申请号：US15693002

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Singidi ,  Ting Luo ,  Ashutosh Malshe ,  Preston Thomson ,  Jianmin Huang

IPC: G11C16/06 ,  G11C16/34 ,  G06F1/30 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G06F1/16

Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.