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公开(公告)号:US09911861B2
公开(公告)日:2018-03-06
申请号:US15224958
申请日:2016-08-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Yutaka Okazaki , Daisuke Matsubayashi , Yuichi Sato
IPC: H01L21/24 , H01L29/786 , H01L29/66 , H01L29/45 , H01L21/441
CPC classification number: H01L29/7869 , H01L21/441 , H01L27/1225 , H01L29/42384 , H01L29/45 , H01L29/66969 , H01L29/7853 , H01L29/78603 , H01L29/78696 , H01L2029/42388
Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.
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公开(公告)号:US09876118B2
公开(公告)日:2018-01-23
申请号:US15450343
申请日:2017-03-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Masahiko Hayakawa , Shinpei Matsuda , Daisuke Matsubayashi
IPC: H01L29/10 , H01L29/12 , H01L29/786 , H01L29/24 , H01L29/04 , H01L29/49 , H01L29/66 , H01L27/12 , H01L27/32 , G02F1/1368
CPC classification number: H01L29/78648 , G02F1/1368 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3262 , H01L29/045 , H01L29/24 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78696
Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 μm or longer and 6.5 μm or shorter.
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公开(公告)号:US09754980B2
公开(公告)日:2017-09-05
申请号:US15193677
申请日:2016-06-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Yusuke Nonaka , Riho Kataishi , Hiroshi Ohki , Yuichi Sato , Daisuke Matsubayashi
IPC: H01L27/146 , H01L31/0224 , H01L31/0272 , H01L31/0296 , H01L31/109
CPC classification number: H01L27/14607 , H01L27/14612 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14647 , H01L27/14665 , H01L27/14694 , H01L27/14696 , H01L31/0224 , H01L31/022475 , H01L31/0272 , H01L31/0296 , H01L31/032 , H01L31/109
Abstract: An imaging device with excellent imaging performance is provided. An imaging device that easily performs imaging under a low illuminance condition is provided. A low power consumption imaging device is provided. An imaging device with small variations in characteristics between its pixels is provided. A highly integrated imaging device is provided. A photoelectric conversion element includes a first electrode, and a first layer, a second layer, and a third layer. The first layer is provided between the first electrode and the third layer. The second layer is provided between the first layer and the third layer. The first layer contains selenium. The second layer contains a metal oxide. The third layer contains a metal oxide and also contains at least one of a rare gas atom, phosphorus, and boron. The selenium may be crystalline selenium. The second layer may be a layer of an In—Ga—Zn oxide including c-axis-aligned crystals.
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公开(公告)号:US09754971B2
公开(公告)日:2017-09-05
申请号:US14276356
申请日:2014-05-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Hiroyuki Miyake , Seiko Inoue , Daisuke Matsubayashi
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1225 , H01L29/78648 , H01L29/7869
Abstract: A semiconductor device includes a dual-gate transistor including an oxide semiconductor film between a first gate electrode and a second gate electrode, a gate insulating film between the oxide semiconductor film and the second gate electrode, and a pair of electrodes in contact with the oxide semiconductor film. The semiconductor device further includes an insulating film over the gate insulating film, and a conductive film over the insulating film and connected to one of the pair of electrodes. The insulating film includes an opening in at least a region overlapping with the oxide semiconductor film in which the second gate electrode is provided in contact with the gate insulating film. The second gate electrode is formed using the same material as the conductive film connected to the one of the pair of electrodes.
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公开(公告)号:US09543295B2
公开(公告)日:2017-01-10
申请号:US14841773
申请日:2015-09-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Yoshitaka Yamamoto , Masayuki Sakakura , Tetsuhiro Tanaka , Daisuke Matsubayashi
IPC: H01L27/07 , H01L29/786 , H01L27/06 , H01L49/02 , H01L23/522 , H01L27/115 , H01L21/8258
CPC classification number: H01L27/0688 , H01L21/8258 , H01L23/5223 , H01L27/1156 , H01L28/40 , H01L29/7869 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
Abstract translation: 提供了包括具有不同阈值电压的晶体管的半导体器件。 或者,提供包括电路的电特性不同的多种电路和晶体管的半导体器件。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管包括氧化物半导体,导体,第一绝缘体,第二绝缘体和第三绝缘体。 导体具有导体和氧化物半导体彼此重叠的区域。 第一绝缘体位于导体和氧化物半导体之间。 第二绝缘体位于导体和第一绝缘体之间。 第三绝缘体位于导体和第二绝缘体之间。 第二绝缘体具有带负电荷的区域。
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公开(公告)号:US09472679B2
公开(公告)日:2016-10-18
申请号:US14594991
申请日:2015-01-12
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Daisuke Matsubayashi , Keisuke Murayama
CPC classification number: H01L29/7869 , H01L29/7831
Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
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公开(公告)号:US09443934B2
公开(公告)日:2016-09-13
申请号:US14480900
申请日:2014-09-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Yoshiyuki Kobayashi , Daisuke Matsubayashi
IPC: H01L29/66 , H01L29/10 , H01L29/786 , H01L29/78
CPC classification number: H01L29/1033 , H01L29/1054 , H01L29/66969 , H01L29/785 , H01L29/7869 , H01L29/78696
Abstract: To provide a transistor having high field effect mobility. To provide a transistor having stable electrical characteristics. To provide a transistor having low off-state current (current in an off state). To provide a semiconductor device including the transistor. The semiconductor device includes a semiconductor; a source electrode and a drain electrode including regions in contact with a top surface and side surfaces of the semiconductor; a gate insulating film including a region in contact with the semiconductor; and a gate electrode including a region facing the semiconductor with the gate insulating film provided therebetween. A length of a region of the semiconductor, which is not in contact with the source and drain electrodes, is shorter than a length of a region of the semiconductor, which is in contact with the source and drain electrodes, in a channel width direction.
Abstract translation: 提供具有高场效应迁移率的晶体管。 提供具有稳定电特性的晶体管。 提供具有低截止电流(截止状态下的电流)的晶体管。 提供包括晶体管的半导体器件。 半导体器件包括半导体; 源电极和漏电极,包括与半导体的顶表面和侧表面接触的区域; 包括与半导体接触的区域的栅极绝缘膜; 以及栅电极,其包括面对半导体的区域,其间设置有栅极绝缘膜。 不与源极和漏极接触的半导体区域的长度比在沟道宽度方向上与源极和漏极接触的半导体的区域的长度短。
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118.
公开(公告)号:US09412764B2
公开(公告)日:2016-08-09
申请号:US14090209
申请日:2013-11-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Hiroyuki Miyake , Daisuke Matsubayashi
CPC classification number: G09G3/3696 , G09G3/3677 , G09G3/3688 , G09G2300/043 , G09G2310/0286 , G09G2320/0214 , G09G2330/00 , H01L27/1225 , H01L27/124
Abstract: To prevent an influence of normally-on characteristics of the transistor which a clock signal is input to a terminal of, a wiring to which a first low power supply potential is appled and a wiring to which a second low power supply potential lower than the first low power supply potential is applied are electrically connected to a gate electrode of the transistor. A semiconductor device including the transistor can operate stably.
Abstract translation: 为了防止输入时钟信号的晶体管的常开特性对其第一低电源电位的端子的施加的第一低电源电位的布线和低于第一低电源电位的第二低电源电位的布线的影响 低电源电位被施加电连接到晶体管的栅电极。 包括晶体管的半导体器件可以稳定地工作。
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119.
公开(公告)号:US09349869B2
公开(公告)日:2016-05-24
申请号:US14060925
申请日:2013-10-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Junichi Koezuka , Yukinori Shima , Hajime Tokunaga , Toshinari Sasaki , Keisuke Murayama , Daisuke Matsubayashi
IPC: H01L29/00 , H01L29/786 , H01L21/02 , H01L29/51 , H01L29/66
CPC classification number: H01L29/66969 , H01L21/022 , H01L21/02263 , H01L27/1225 , H01L29/513 , H01L29/78609 , H01L29/7869
Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
Abstract translation: 为了减少半导体器件中的氧化物半导体膜的缺陷。 为了改善包括氧化物半导体膜的半导体器件的电特性和可靠性。 在包括晶体管的半导体器件中,所述晶体管包括形成在衬底上的栅电极,覆盖栅电极的栅极绝缘膜,与栅电极重叠的多层膜,栅极绝缘膜设置在其间;以及一对电极, 多层膜,覆盖晶体管的第一氧化物绝缘膜和形成在第一氧化物绝缘膜上的第二氧化物绝缘膜,多层膜包括氧化物半导体膜和含有In或Ga的氧化物膜,第一氧化物绝缘膜为 氧透过氧化物绝缘膜,第二氧化物绝缘膜是比化学计量组合物含有氧更多的氧化物绝缘膜。
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公开(公告)号:US09318484B2
公开(公告)日:2016-04-19
申请号:US14179892
申请日:2014-02-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Daisuke Matsubayashi
CPC classification number: H01L27/105 , H01L27/0629 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L29/16 , H01L29/78 , H01L29/7869
Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.
Abstract translation: 本发明的半导体器件包括第一和第二晶体管以及第一和第二电容器。 第一晶体管的源极和漏极之一电连接到第一布线,另一个电连接到第二布线,并且第一晶体管的栅电极电连接到源电极和漏电极中的一个 第二晶体管和第一电容器的电极中的一个。 第二晶体管的源极和漏极中的另一个电连接到第一布线,并且第二晶体管的栅电极电连接到第二电容器的电极和第五布线之一。 第一电容器的另一个电极电连接到第三布线,第二电容器的另一个电极折叠地连接到第四布线。
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