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214 条记录 (耗时 0.044 秒)

    Economical, scalable transceiver jitter test
    112.
    发明申请
    Economical, scalable transceiver jitter test 有权
    经济，可扩展的收发器抖动测试

    公开(公告)号：US20080013609A1

    公开(公告)日：2008-01-17

    申请号：US11484986

    申请日：2006-07-11

    申请人： Kenneth T. Daxer ,  Sergey Shumarayev

    发明人： Kenneth T. Daxer ,  Sergey Shumarayev

    IPC分类号： H04L5/16 ,  H04B3/46

    CPC分类号： H04B3/46 ,  H04L1/205 ,  H04L1/243

    摘要： Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram), which is equivalent to the amplitude of the jitter, is used to filter out bad transceiver units.

    摘要翻译： 任何数量的收发器通道同时测试抖动生成/容差。 经测试的通道使用串行回送路径将收发器发送通道连接到收发器接收器通道。 发射机和接收机PLL均连接到公共参考时钟。 参考时钟以低于发射机PLL的带宽但高于接收机PLL的带宽的频率的抖动进行调制。 眼睛闭合的大小（在眼图中）相当于抖动的幅度，用于滤除不良收发器单元。

    Programmable digital equalization control circuitry and methods
    115.
    发明申请
    Programmable digital equalization control circuitry and methods 失效
    可编程数字均衡控制电路和方法

    公开(公告)号：US20070071084A1

    公开(公告)日：2007-03-29

    申请号：US11238365

    申请日：2005-09-28

    申请人： Tin Lai ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong

    发明人： Tin Lai ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong

    IPC分类号： H03H7/30 ,  H04L25/06 ,  H04L27/08

    CPC分类号： H03G3/3089 ,  H04L25/03885

    摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.

    摘要翻译： 均衡电路可用于补偿由传输介质引起的数据信号的衰减。 用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。 比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。 可编程上/下计数器可以根据比较器的输出来调整计数器值。 可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。 这些模拟电压可以作为控制输入提供给均衡级。 控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。

    Dynamically adjustable termination impedance control techniques
    116.
    发明授权
    Dynamically adjustable termination impedance control techniques 有权
    动态可调终端阻抗控制技术

    公开(公告)号：US07176710B1

    公开(公告)日：2007-02-13

    申请号：US11093188

    申请日：2005-03-28

    申请人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03K19/175

    CPC分类号： H04L25/0278

    摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

    摘要翻译： 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

    Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths
    117.
    发明授权
    Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths 有权
    时钟数据恢复电路和具有动态可调节带宽的锁相环电路

    公开(公告)号：US07149914B1

    公开(公告)日：2006-12-12

    申请号：US10672901

    申请日：2003-09-26

    申请人： Kazi Asaduzzaman ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Kazi Asaduzzaman ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/24

    CPC分类号： H03L7/087 ,  H03L7/107 ,  H03L7/18 ,  H04L7/0008 ,  H04L7/033

    摘要： Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

    摘要翻译： 时钟数据恢复（CDR）电路或锁相环（PLL）电路可以提供动态可调的带宽。 可以提供一个CDR电路或PLL电路以支持多个系统或协议，给定系统或协议的多个参数要求，以及给定系统或协议内的输入频率或数据速率的变化。 这些参数可以包括抖动（例如，抖动容限，抖动传输，抖动产生），主要噪声源和锁定时间。 当电路正在处理数据时，控制信号可用于动态调整CDR电路或PLL电路的带宽。 控制信号可以由PLD，处理器，PLD外部的电路或用户输入来设置。

    Adjustable differential input and output drivers
    119.
    发明授权
    Adjustable differential input and output drivers 失效
    可调差分输入和输出驱动器

    公开(公告)号：US06972588B1

    公开(公告)日：2005-12-06

    申请号：US11029275

    申请日：2005-01-05

    申请人： Wilson Wong ,  Sergey Shumarayev

    发明人： Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03K19/0185 ,  H04L25/02 ,  H03K17/16

    CPC分类号： H04L25/0276 ,  H03K19/018564

    摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

    摘要翻译： 使用共模电压偏置电路提供系统和方法，以对集成电路差分通信链路中的差分驱动器电路进行共模电压调整。 可调节的偏置电路可以使用静态和动态控制信号来控制。 动态控制信号可以由可编程逻辑器件或其他集成电路上的核心逻辑产生。 静态控制信号可以由可编程元件产生。 差分链路一端进行的偏置电路调整可用于提高链路两端的性能，或者可用于提高功耗或平衡功率和性能考虑。 同样的集成电路设计可用于交流耦合和直流耦合环境。 偏置电路可以由可调电流源和可调电阻器形成。 电流源和可调电阻可由相同的控制信号控制。

    Integrated circuit devices with power supply detection circuitry
    120.
    发明申请
    Integrated circuit devices with power supply detection circuitry 失效
    具有电源检测电路的集成电路器件

    公开(公告)号：US20050040863A1

    公开(公告)日：2005-02-24

    申请号：US10753056

    申请日：2004-01-06

    申请人： Sergey Shumarayev ,  Thomas White

    发明人： Sergey Shumarayev ,  Thomas White

    IPC分类号： G06F1/24 ,  G06F1/28 ,  H03K5/22

    CPC分类号： H03K17/22 ,  G06F1/24 ,  G06F1/28

    摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

    摘要翻译： 提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。 功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。 良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。 来自功率检测电路的输出可以与控制信号组合，用于各种应用。 应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。