公开(公告)号：US07149914B1

公开(公告)日：2006-12-12

申请号：US10672901

申请日：2003-09-26

申请人： Kazi Asaduzzaman ,  Wilson Wong ,  Sergey Shumarayev

发明人： Kazi Asaduzzaman ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/24

CPC分类号： H03L7/087 ,  H03L7/107 ,  H03L7/18 ,  H04L7/0008 ,  H04L7/033

摘要： Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

摘要翻译： 时钟数据恢复（CDR）电路或锁相环（PLL）电路可以提供动态可调的带宽。 可以提供一个CDR电路或PLL电路以支持多个系统或协议，给定系统或协议的多个参数要求，以及给定系统或协议内的输入频率或数据速率的变化。 这些参数可以包括抖动（例如，抖动容限，抖动传输，抖动产生），主要噪声源和锁定时间。 当电路正在处理数据时，控制信号可用于动态调整CDR电路或PLL电路的带宽。 控制信号可以由PLD，处理器，PLD外部的电路或用户输入来设置。

公开(公告)号：US08120429B1

公开(公告)日：2012-02-21

申请号：US12787722

申请日：2010-05-26

申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L7/00 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US07728674B1

公开(公告)日：2010-06-01

申请号：US11437558

申请日：2006-05-19

申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US20070013411A1

公开(公告)日：2007-01-18

申请号：US11183288

申请日：2005-07-14

申请人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

发明人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H03K19/094

CPC分类号： H03K17/164

摘要： High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.

摘要翻译： 可能需要高速变送器驱动器和其他类型的驱动电路来产生具有可变转换速率的输出信号。 描述了用于提供可变转换速率控制的驱动电路和方法。 可以使用具有可变转换速率的前驱动器电路在驱动器输入端提供具有可变转换速率的信号。 驱动器和/或预驱动器电路可以包括具有可变驱动强度的晶体管。 驱动器和/或预驱动器电路还可以包括用于改变电路驱动强度的可选择地启用的级。 预驱动器电路可以被延迟匹配以保持信号质量。 还描述了其它电路和方法。

公开(公告)号：US08811555B2

公开(公告)日：2014-08-19

申请号：US12700433

申请日：2010-02-04

申请人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

发明人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC分类号： H04L7/00 ,  H03L7/081 ,  H04L7/033 ,  H03L7/08

CPC分类号： H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).

摘要翻译： 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

公开(公告)号：US07619451B1

公开(公告)日：2009-11-17

申请号：US11670971

申请日：2007-02-03

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  G06F1/12 ,  H03L7/081 ,  H03L7/0812

摘要： Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

摘要翻译： 提供了用于补偿由集成电路上的锁相环和延迟锁定环路产生的时钟信号中的相位和定时延迟的技术。 耦合在锁定电路的反馈回路中的电路元件可以补偿输入引脚和输出引脚之间的定时和相位延迟。 耦合在锁定电路的反馈环路中的其它电路元件可以补偿输入引脚和目的地电路元件之间的延迟。 耦合在锁定电路的输入参考路径中的其他电路元件保留输入时钟和输入数据信号之间的定时关系。 在目的地电路元件处接收的时钟信号和数据信号在输入引脚的输入时钟和输入数据信号之间具有相同的相位和定时关系。

公开(公告)号：US20110188621A1

公开(公告)日：2011-08-04

申请号：US12700433

申请日：2010-02-04

申请人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

发明人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC分类号： H04L7/00

CPC分类号： H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

摘要翻译： 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。 这可以帮助IC支持采用自动速度协商的通信协议。

公开(公告)号：US07532029B1

公开(公告)日：2009-05-12

申请号：US11737079

申请日：2007-04-18

申请人： Kazi Asaduzzaman ,  Leon Zheng ,  Sergey Shumarayev ,  Tim Tri Hoang

发明人： Kazi Asaduzzaman ,  Leon Zheng ,  Sergey Shumarayev ,  Tim Tri Hoang

IPC分类号： H03K19/173 ,  H03L7/00

CPC分类号： H03K19/1733 ,  H03K19/17752 ,  H03L7/081 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/0996 ,  H03L7/18

摘要： Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.

摘要翻译： 提供技术用于在用户模式期间动态地重新配置集成电路上的可编程电路块。 在配置模式下，第一个配置位从第一个配置扫描寄存器加载到第二个配置扫描寄存器中。 第一个配置位用于配置可编程电路块的可编程设置。 在用户模式期间，第二配置位从引脚传输到第二配置扫描寄存器，而不通过第一配置扫描寄存器传输第二配置位。 第二个配置位用于在用户模式期间重新配置可编程电路块的可编程设置。 此外，相移电路可以通过选择不同的输入时钟信号来动态地移位输出时钟信号的相位。 相移电路具有允许高频时钟信号的相位被移位而不引起时钟信号的毛刺的延迟电路。

公开(公告)号：US08416001B2

公开(公告)日：2013-04-09

申请号：US13083431

申请日：2011-04-08

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

摘要翻译： 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC分类号： H03F1/26

CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。