公开(公告)号：US10204981B2

公开(公告)日：2019-02-12

申请号：US15656802

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Ching-Ling Lin

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

公开(公告)号：US20180374757A1

公开(公告)日：2018-12-27

申请号：US16127241

申请日：2018-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/308

Abstract: A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure.

公开(公告)号：US10163659B1

公开(公告)日：2018-12-25

申请号：US15654552

申请日：2017-07-19

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L21/48 ,  H01L21/8234 ,  H01L29/66

Abstract: A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.

公开(公告)号：US20180331219A1

公开(公告)日：2018-11-15

申请号：US15627427

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L27/088 ,  H01L29/6656

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

公开(公告)号：US20180260510A1

公开(公告)日：2018-09-13

申请号：US15479271

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Chien-Ting Ho ,  Li-Wei Feng ,  Emily SH Huang

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/108

CPC classification number: G06F17/5077 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

公开(公告)号：US10062613B1

公开(公告)日：2018-08-28

申请号：US15611759

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823456 ,  H01L21/82345 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function metal layer in the first trench and the second trench; forming a patterned mask to cover the second trench; removing the first work function metal layer from the first trench; forming a second work function metal layer in the first trench and the second trench; and forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US20180203344A1

公开(公告)日：2018-07-19

申请号：US15436764

申请日：2017-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chia-Hung Lin

IPC: G03F1/58 ,  G03F1/54

CPC classification number: G03F1/58 ,  G03F1/54

Abstract: A photomask includes a substrate, a patterned absorber layer disposed on the substrate, and a plurality of openings. Each of the openings penetrates the patterned absorber layer and exposes a part of the substrate. At least two of the openings are disposed adjacent to each other in a first direction. At least a part of the patterned absorber layer disposed between the two adjacent openings in the first direction has a first thickness. A part of the patterned absorber layer disposed at two opposite edges of each of the openings in a second direction different from the first direction has a second thickness. Another part of the patterned absorber layer disposed at the two opposite edges of each of the openings in the second direction has a third thickness. The first thickness is equal to the second thickness, and the first thickness is different from the third thickness.

公开(公告)号：US20180149978A1

公开(公告)日：2018-05-31

申请号：US15361085

申请日：2016-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/308 ,  G03F7/40

CPC classification number: H01L21/0274 ,  G03F7/0035 ,  G03F7/203

Abstract: A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. A first mask includes first line patterns and a first block pattern. A second mask includes second line patterns and a second block pattern. Two photolithography processes with the first mask and the second mask are performed for forming a patterned structure including first line structures and second line structures. Each first line structure is elongated in the first direction. The first line structures are defined by a region where the first line patterns and the second block pattern overlap with one another. Each second line structure is elongated in the second direction. The second line structures are defined by a region where the second line patterns and the first block pattern overlap with one another.

公开(公告)号：US09960163B2

公开(公告)日：2018-05-01

申请号：US15134367

申请日：2016-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L21/306

CPC classification number: H01L27/0924 ,  H01L21/30625 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/267

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first fin-shaped structure and a bump are formed on the substrate, and an insulating layer is formed on the bump and around the first fin-shaped structure. Next, a part of the first fin-shaped structure is removed, an epitaxial layer is formed on the first fin-shaped structure, part of the epitaxial layer is removed, and part of the insulating layer is removed to form a shallow trench isolation (STI) and a second fin-shaped structure protruding from the STI. Preferably, the second fin-shaped structure includes a top portion and a bottom portion, in which the bottom portion and the bump are made of same material.

公开(公告)号：US20180097109A1

公开(公告)日：2018-04-05

申请号：US15832755

申请日：2017-12-05

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.