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250 条记录 (耗时 0.052 秒)

    Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics
    111.
    发明授权
    Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics 有权
    集成电路级间介质中氮氧化硅薄膜的分层还原

    公开(公告)号：US06133619A

    公开(公告)日：2000-10-17

    申请号：US144521

    申请日：1998-08-31

    申请人： Kashmir Sahota ,  Richard J. Huang ,  David Matsumoto ,  Mark T. Ramsbey ,  Yu Sun ,  Judith Quan Rizzuto

    发明人： Kashmir Sahota ,  Richard J. Huang ,  David Matsumoto ,  Mark T. Ramsbey ,  Yu Sun ,  Judith Quan Rizzuto

    IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L51/00

    CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/3124 ,  H01L21/3145

    摘要： Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.

    摘要翻译： 从介电间隙填充层，例如低介电常数材料（例如HSQ）以及随后的热处理过程中覆盖的图案化导电层上的阻挡介电层的伴随变形或分层的脱气被避免或显着减少，通过控制 电介质间隙填充层上的介电覆盖层。 实施例包括在第一导电图案上沉积保形SiON阻挡层，在保形SiON阻挡层上沉积HSQ间隙填充层，沉积氧化硅覆盖层并进行平坦化，使得平坦化硅覆盖层的厚度为至少2500， 从而避免在随后的热处理期间覆盖的图案化导电层上的保形SiON阻挡层的变形和/或分层。

    Non-volatile trench semiconductor device
    112.
    发明授权
    Non-volatile trench semiconductor device 失效
    非易失性沟槽半导体器件

    公开(公告)号：US6002151A

    公开(公告)日：1999-12-14

    申请号：US993890

    申请日：1997-12-18

    申请人： Yowjuang William Liu ,  Yu Sun ,  Donald L. Wollesen

    发明人： Yowjuang William Liu ,  Yu Sun ,  Donald L. Wollesen

    IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/88 ,  H01L29/92

    CPC分类号： H01L27/11521 ,  H01L29/42336 ,  H01L29/7883

    摘要： A non-volatile memory device is formed in a substrate, thereby enabling increased densification. Embodiments include forming a trench in a substrate, forming a substantially U-shaped tunnel dielectric layer in the trench, depositing a substantially U-shaped floating gate electrode on the tunnel dielectric layer, forming a dielectric layer on the floating gate electrode extending on the substrate surface and forming a substantially T-shaped control gate electrode filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form source/drain regions extending into the substrate to substantially the same depth, leaving a region containing an impurity of the first conductivity type at the intersection of the trench and substrate surface which prevents shorting between the source/drain region and gate electrodes.

    摘要翻译： 在基板中形成非易失性存储器件，从而能够增加致密化。 实施例包括在衬底中形成沟槽，在沟槽中形成基本为U形的隧道介电层，在隧道介电层上沉积基本为U形的浮动栅电极，在衬底上延伸的浮栅上形成电介质层 并且形成填充沟槽并在衬底上延伸的基本上T形的控制栅电极。 侧壁间隔物形成在控制栅电极和电介质层的侧表面上，然后进行离子注入，以形成延伸到衬底中的基本相同深度的源极/漏极区域，在相交处留下含有第一导电类型杂质的区域 的沟槽和衬底表面，防止源极/漏极区域和栅电极之间的短路。

    Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch
    113.
    发明授权
    Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch 失效
    保护半导体器件中的堆叠栅极边缘的方法不受自对准源（SAS）蚀刻

    公开(公告)号：US5470773A

    公开(公告)日：1995-11-28

    申请号：US233174

    申请日：1994-04-25

    申请人： David K. Y. Liu ,  Yu Sun ,  Chi Chang

    发明人： David K. Y. Liu ,  Yu Sun ,  Chi Chang

    IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  H01L27/11536

    摘要： A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

    摘要翻译： 公开了一种用于保护半导体器件的堆叠栅极边缘的工艺。 该方法提供在完成自对准源（SAS）蚀刻之前提供间隔物形成。 通过在SAS蚀刻之前提供间隔物形成，隧道氧化物完整性得到很大改善，并且源极结注入轮廓更均匀，因为源区周围的硅不会被去除。

    Learning state-dependent sensor measurement models for localization
    115.
    发明授权
    Learning state-dependent sensor measurement models for localization 有权

    公开(公告)号：US10572802B1

    公开(公告)日：2020-02-25

    申请号：US16236715

    申请日：2018-12-31

    申请人： Yu Sun ,  Troi Williams

    发明人： Yu Sun ,  Troi Williams

    IPC分类号： G06N3/04 ,  G06N3/08 ,  G06N7/00

    摘要： A noise and bias can be determined for a sensor. An input vector can be received. A parameter vector can be generated based at least in part on a feed-forward neural network. Components can be determined using the parameter vector based at least in part on a mixture model. A conditional probability density function can be generated based at least in part on the conditional probability density function.

    Generating robotic trajectories with motion harmonics
    116.
    发明授权
    Generating robotic trajectories with motion harmonics 有权

    公开(公告)号：US09764469B1

    公开(公告)日：2017-09-19

    申请号：US14568755

    申请日：2014-12-12

    申请人： Yu Sun ,  Yuongqiang Huang

    发明人： Yu Sun ,  Yuongqiang Huang

    IPC分类号： G05B19/18 ,  B25J9/16

    CPC分类号： B25J9/1664 ,  G05B2219/36422 ,  G05B2219/40391 ,  G05B2219/40431

    摘要： Aspects of the generation of new robotic motion trajectories are described. In one embodiment, a new robot motion trajectory may be generated by gathering demonstrated motion trajectories, adapting the demonstrated motion trajectories into robot-reachable motion trajectories based on a joint space of a robot model, for example, and generating motion harmonics with reference to the motion trajectories. Further, one or more constraints may be specified for a new goal. The weights of the motion harmonics may then be searched to identify or generate a new motion trajectory for a robot, where the new motion minimizes discrepancy from the demonstrated motion trajectories and error due to the at least one constraint. In the new motion trajectory, the degree to which the constraints are satisfied may be tuned using a weight. According to the embodiments, new motion variants may be generated without the need to learn or review new demonstrated trajectories.