公开(公告)号：US20060172620A1

公开(公告)日：2006-08-03

申请号：US11344847

申请日：2006-02-01

申请人： Yutaka Noro ,  Ryotaro Ishikawa ,  Hajime Kawase ,  Keiichi Nakamura ,  Yutaka Kobayashi

发明人： Yutaka Noro ,  Ryotaro Ishikawa ,  Hajime Kawase ,  Keiichi Nakamura ,  Yutaka Kobayashi

IPC分类号： H01R13/11

CPC分类号： H01R13/113 ,  H01R13/422 ,  H01R43/16

摘要： A terminal fitting has a rectangular tube (10) formed with a locking hole (19). A resilient contact piece (25) is in the rectangular tube (10) for contacting a tab of a mating terminal fitting. Displacement restricting portions (15F, 15R, 18F, 18R) are provided in the rectangular tube (10) at positions before and behind the locking hole (19) for contacting lateral edges of the resilient contact piece (25) and restricting displacement of a resilient contact piece (25) towards a tab entrance space (32). Thus, external matter that may intrude through the locking hole (19) can not cause a damaging deformation of the resilient contact piece (25).

摘要翻译： 端子接头具有形成有锁定孔（19）的矩形管（10）。 弹性接触片（25）位于矩形管（10）中，用于接触配合端子接头的接头。 在矩形管（10）中的位于锁定孔（19）前后的位置处设有位移限制部（15F，15R，18F，18R），用于接触弹性接触片（25）的横向边缘并限制 弹性接触片（25）朝向突片入口空间（32）的位移。 因此，可能通过锁定孔（19）侵入的外部物质不会导致弹性接触片（25）的破坏性变形。

公开(公告)号：US20050179209A1

公开(公告)日：2005-08-18

申请号：US11096100

申请日：2005-03-31

申请人： Yutaka Kobayashi

发明人： Yutaka Kobayashi

IPC分类号： F16J13/02 ,  F16J15/02 ,  F16J15/06 ,  H01R13/443 ,  H01R13/52 ,  F16J15/32

CPC分类号： H01R13/521 ,  F16J13/02 ,  F16J15/025 ,  F16J15/062 ,  H01R13/443 ,  H01R13/5219

摘要： A dummy plug (20) is formed with only one lip (25) having a wide outer surface (26) with a fine undulated pattern (30) that has repeated projections (31) of short height. The projections (31) are disposed to be tangent to a plane. Inclined surfaces (27) are formed at opposite ends of the outer surface (26). The inclined surface (27) guides the dummy plug (20) centrally into a cavity (11) while the outer surface (26) is compressed uniformly and resiliently over the entire circumference. The outer surface (26) closely contacts the inner surface of the cavity (11) due to a resilient force, thereby sealing the cavity (11). The fine undulated pattern (30) decreases the contact area and hence decreases the frictional resistance. Thus, the dummy plug (20) can be inserted smoothly inserted into the cavity (11) with a smaller force.

摘要翻译： 虚拟插头（20）形成有仅具有宽的外表面（26）的一个唇部（25），其具有具有短高度的重复突起（31）的细小的波纹图案（30）。 突起（31）设置成与平面相切。 倾斜表面（27）形成在外表面（26）的相对端。 倾斜表面（27）将虚拟插头（20）中心地引导到空腔（11）中，同时外表面（26）在整个圆周上被均匀地和弹性地压缩。 由于弹性力，外表面（26）紧密地接触空腔（11）的内表面，从而密封空腔（11）。 精细波纹图案（30）减小接触面积，从而降低摩擦阻力。 因此，可以以较小的力将虚拟插头（20）平滑地插入空腔（11）中。

公开(公告)号：US06670734B2

公开(公告)日：2003-12-30

申请号：US10011058

申请日：2001-12-06

申请人： Satoshi Morishima ,  Kyoshi Kawamoto ,  Yutaka Kobayashi

发明人： Satoshi Morishima ,  Kyoshi Kawamoto ,  Yutaka Kobayashi

IPC分类号： H02K706

CPC分类号： H02K7/06 ,  F16H25/2015 ,  F16H25/2021 ,  F16H25/2204 ,  H02K11/27 ,  Y10T74/18592

摘要： A linear actuator includes a screw shaft rotatably supported within a housing with play in motion in the axial direction of the screw shaft, and a cushioning stopper disposed between the housing and the screw shaft and elastically deformable to absorb a force acting from the screw shaft to the housing when the screw shaft is forced to move relative to the housing in the axial direction within the range of the play at an abutment of a rod with an obstacle or stopper. When the rod is stopped moving, the motor current increases with the degree of elastic deformation of the cushioning stopper. An overload sensor cuts off the supply of power to an electric motor when excessive current in the motor is detected.

公开(公告)号：US06589083B2

公开(公告)日：2003-07-08

申请号：US10095666

申请日：2002-03-11

申请人： Yutaka Kobayashi ,  Hajime Kawase ,  Ryotaro Ishikawa

发明人： Yutaka Kobayashi ,  Hajime Kawase ,  Ryotaro Ishikawa

IPC分类号： H01R13436

CPC分类号： H01R13/4362

摘要： A connector housing (10) has cavities (23) and a retainer insertion hole (27) that crosses the cavities (23). A retainer (30) can be held at a partial or full locking position in the retainer insertion hole (27). The retainer (30) has pairs of resilient locks (33) and fixed locks (35) for the corresponding cavities (23). The resilient locks (33) project into the cavities (23) when the retainer (30) is at the partial locking position while the fixed locks (35) project into the cavities,(23) when the retainer (30) is at the full locking position. The resilient locks (33) are wider than the cavities (23) and hence continue engaging the terminal fittings (10) while the retainer (30) is moved from the partial locking position to the full locking position. Thus, the terminal fittings (10) are locked doubly by the fixed locks (33) and parts of the resilient locks (33) when the retainer (30) is at the full locking position.

摘要翻译： 连接器壳体（10）具有空腔（23）和与空腔（23）相交的保持器插入孔（27）。 保持器（30）可以保持在保持器插入孔（27）中的部分或完全锁定位置。 保持器（30）具有成对的用于相应空腔（23）的弹性锁（33）和固定锁（35）。 当保持器（30）处于充满状态时，当保持器（30）处于部分锁定位置时，当固定锁（35）突出到空腔（23）中时，弹性锁（33）突出到空腔（23） 锁定位置。 弹性锁（33）比空腔（23）更宽，并且因此在保持器（30）从部分锁定位置移动到完全锁定位置的同时继续接合端子接头（10）。 因此，当保持器（30）处于完全锁定位置时，端子接头（10）被固定锁（33）和弹性锁（33）的一部分双重锁定。

公开(公告)号：US06239628B1

公开(公告)日：2001-05-29

申请号：US09245897

申请日：1999-02-08

申请人： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Yutaka Kobayashi

发明人： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Yutaka Kobayashi

IPC分类号： H04L700

CPC分类号： G06F9/3869

摘要： A semiconductor integrated circuit device is dislosed for self-monitoring presence/absence of a data flow and transmitting the data on the basis of the result of the monitoring. The semiconductor integrated circuit device comprises a plurality of data paths each further comprising at least two logic-circuit blocks. One of the data paths have data-arrival detector for detecting arrival of data and components on the other data paths operate synchronously with those on the data path having the data-arrival detector.

摘要翻译： 半导体集成电路装置被断开，用于自我监测数据流的存在/不存在，并且基于监视结果发送数据。 半导体集成电路装置包括多个数据路径，每个数据路径还包括至少两个逻辑电路块。 数据路径之一具有数据到达检测器，用于检测其他数据路径上的数据和组件的到达与具有数据到达检测器的数据路径上的数据到达检测器同步操作。

公开(公告)号：US06208010B1

公开(公告)日：2001-03-27

申请号：US08574110

申请日：1995-12-18

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US06206671B1

公开(公告)日：2001-03-27

申请号：US09243420

申请日：1999-02-03

申请人： Masatoshi Tsuchiya ,  Atsushi Mogami ,  Yutaka Kobayashi ,  Hideki Ohno ,  Masato Sekino

发明人： Masatoshi Tsuchiya ,  Atsushi Mogami ,  Yutaka Kobayashi ,  Hideki Ohno ,  Masato Sekino

IPC分类号： A61C1300

CPC分类号： A61C13/20

摘要： A pressure molding apparatus comprises a furnace defining a heating space for accommodating a mold assembly including a mold body charged with a raw material to be molded, and a pressure piston for pressurizing the raw material; heating means for heating the heating space; and load imposing means for imposing a load on the pressure piston to mold the raw material. The load imposing means includes at least one weight means and weight supporting means. The weight supporting means is selectively set in a load-free state in which the weight supporting means supports the weight means so that the weight of the weight means is not imposed on the pressure piston, and a load imposed state in which the weight supporting means releases the support of the weight means so that the weight of the weight means is imposed on the pressure piston.

摘要翻译： 压力成型装置包括限定用于容纳模具组件的加热空间的炉子，该模具组件包括装有待成型原料的模具体和用于对原料加压的压力活塞; 用于加热加热空间的加热装置; 以及用于在压力活塞上施加负载以模制原材料的负载施加装置。 载荷施加装置包括至少一个重量装置和重量支撑装置。 重量支撑装置被选择性地设置在无负载状态，其中重量支撑装置支撑重量装置，使得重量装置的重量不施加在压力活塞上，以及负载施加状态，其中重量支撑装置 释放重量装置的支撑，使重量装置的重量施加在压力活塞上。

公开(公告)号：US6020638A

公开(公告)日：2000-02-01

申请号：US103540

申请日：1998-06-24

申请人： Yutaka Kobayashi

发明人： Yutaka Kobayashi

IPC分类号： H01L23/12 ,  H05K1/03 ,  H05K3/28 ,  H05K3/34 ,  H01L23/48

CPC分类号： H05K3/284 ,  H05K1/0306 ,  H05K3/3436

摘要： A packaging structure of a semiconductor device having a BGA type package structure. The packaging structure has a circuit substrate for mounting a semiconductor device having a BGA type package structure thereon, a semiconductor device having the BGA type package structure in which BGA balls that are external terminals are electrically connected to the circuit substrate, and insulating resin charged between the circuit substrate and the semiconductor device.

摘要翻译： 具有BGA型封装结构的半导体器件的封装结构。 封装结构具有用于安装其上具有BGA型封装结构的半导体器件的电路基板，具有BGA型封装结构的半导体器件，其中外部端子的BGA球与电路基板电连接， 电路基板和半导体器件。

公开(公告)号：US5917211A

公开(公告)日：1999-06-29

申请号：US979543

申请日：1997-11-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  H01L21/823425

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

摘要翻译： 一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。 当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

公开(公告)号：US5731219A

公开(公告)日：1998-03-24

申请号：US458616

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

摘要翻译： 这里公开了一种半导体集成电路器件，其特征在于包括SRAM，其SRAM具有通过字线和驱动MISFET来控制的转移MISFET构成的存储单元，以及形成该器件的方法。 驱动MISFET的栅电极和存储单元的转移MISFET以及字线分别由不同的导电层形成。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 源极线由与字线的导电层相同的导电层形成。 在驱动MISFET的栅电极上形成抗氧化膜，以减少由这些栅电极的边缘部分的氧化引起的应力，并减少产生的漏电流。 形成在转移MISFET和字线的栅电极上的氧化膜的厚度比形成在驱动MISFET的栅电极上的氧化膜厚，使得数据线焊盘可以形成为与氧化膜和侧面自对准 传输MISFET的栅电极上的壁间隔物。