公开(公告)号：US10044009B2

公开(公告)日：2018-08-07

申请号：US15260008

申请日：2016-09-08

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/06 ,  H01M10/04 ,  H01M2/10 ,  H01M2/04 ,  H01M2/20 ,  H01M2/30

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US09991341B2

公开(公告)日：2018-06-05

申请号：US15363616

申请日：2016-11-29

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Arnaud Yvon

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/322 ,  H01L29/20 ,  H01L29/66 ,  H01L29/36 ,  H01L29/872

CPC classification number: H01L29/0661 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/30612 ,  H01L21/30621 ,  H01L21/30625 ,  H01L21/3228 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66212 ,  H01L29/872

Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.

公开(公告)号：US20180130608A1

公开(公告)日：2018-05-10

申请号：US15862752

申请日：2018-01-05

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley

IPC: H01G7/06 ,  H03H5/12 ,  H03H7/01 ,  G01R15/16 ,  G05F5/00 ,  H04B1/04

CPC classification number: H01G7/06 ,  G01R15/165 ,  G05F5/00 ,  H03H5/12 ,  H03H7/0153 ,  H04B1/0458

Abstract: A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

公开(公告)号：US20180130607A1

公开(公告)日：2018-05-10

申请号：US15862707

申请日：2018-01-05

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley

IPC: H01G7/06 ,  H03H5/12 ,  H03H7/01 ,  G01R15/16 ,  G05F5/00 ,  H04B1/04

CPC classification number: H01G7/06 ,  G01R15/165 ,  G05F5/00 ,  H03H5/12 ,  H03H7/0153 ,  H04B1/0458

Abstract: A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

公开(公告)号：US09899153B2

公开(公告)日：2018-02-20

申请号：US14964654

申请日：2015-12-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley

IPC: H01G7/06 ,  G01R15/16 ,  G05F5/00 ,  H03H5/12 ,  H03H7/01 ,  H04B1/04

CPC classification number: H01G7/06 ,  G01R15/165 ,  G05F5/00 ,  H03H5/12 ,  H03H7/0153 ,  H04B1/0458

Abstract: A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

公开(公告)号：US20170288044A1

公开(公告)日：2017-10-05

申请号：US15362919

申请日：2016-11-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/747 ,  H01L29/408 ,  H01L29/66386

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

公开(公告)号：US20170287893A1

公开(公告)日：2017-10-05

申请号：US15252964

申请日：2016-08-31

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu Rouviere ,  Arnaud Florence

IPC: H01L27/02 ,  H01L23/31 ,  H01L49/02 ,  H01L27/06 ,  H01L29/866

CPC classification number: H01L27/0248 ,  H01L23/3114 ,  H01L27/0255 ,  H01L27/0676 ,  H01L28/40 ,  H01L29/866

Abstract: An electrostatic discharge protection device includes first and second diodes series-connected between first and second connection terminals. A third connection terminal is coupled to a junction of the first and second diodes. A capacitor is connected in parallel with the first and second diodes between the first and second terminals.

公开(公告)号：US20170230002A1

公开(公告)日：2017-08-10

申请号：US15252868

申请日：2016-08-31

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley ,  Jerome Heurtier ,  Laurent Jeuffrault

IPC: H03B5/20

CPC classification number: H03B5/20 ,  H01G7/06 ,  H03B5/124 ,  H03B2201/011 ,  H03L7/1075

Abstract: A first capacitor has a capacitance adjustable to a set point value by application of a bias voltage. A second capacitor also has a capacitance adjustable to a set point value by application of a bias voltage. The first and second capacitors are arranged to receive the same bias voltage generated by a control circuit. The control circuit receiving the set point value as an input and generates that bias voltage in response to a quantity representative of a capacitance of the second capacitor.

公开(公告)号：US09543247B1

公开(公告)日：2017-01-10

申请号：US15051158

申请日：2016-02-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory

IPC: H01L23/52 ,  H01L29/06 ,  H01L29/16 ,  H01L23/528 ,  H01L21/306 ,  H01L21/304 ,  H01L21/302 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/76843 ,  H01L21/302 ,  H01L21/3043 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0657 ,  H01L29/16 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an external device. The metallization has a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate. A porous silicon region is included in the substrate to separating the second portion of the metallization from the rest of the substrate.

Abstract translation: 表面安装芯片由具有正面和侧面的硅基板形成。 芯片包括用于焊接到外部设备的金属化。 金属化具有覆盖基板的前表面的至少一部分的第一部分和覆盖基板侧面的至少一部分的第二部分。 衬底中包括多孔硅区域以将金属化的第二部分与衬底的其余部分分离。

公开(公告)号：US09525361B2

公开(公告)日：2016-12-20

申请号：US14826627

申请日：2015-08-14

Applicant: STMicroelectronics (Tours) SAS

Inventor： Laurent Gonthier

IPC: H02M7/00 ,  H02M7/06 ,  H02M7/162 ,  H02M1/08 ,  H02M7/155

CPC classification number: H02M7/06 ,  H02M1/081 ,  H02M7/155 ,  H02M7/1623

Abstract: A rectifying circuit includes a first diode coupled between a first terminal configured to receive application of an A.C. voltage and a first terminal configured to deliver a rectified voltage; and an anode-gate thyristor coupled between a second terminal configured to receive application of the A.C. voltage and a second terminal configured to deliver the rectified voltage, wherein an anode of the anode-gate thyristor is connected to the second terminal configured to deliver the rectified voltage.

Abstract translation: 整流电路包括耦合在被配置为接收交流电压的施加的第一端子和被配置为传送整流电压的第一端子之间的第一二极管; 以及耦合在被配置为接收所述AC电压的施加的第二端子和被配置为传送整流电压的第二端子之间的阳极栅极晶闸管，其中所述阳极栅极晶闸管的阳极连接到所述第二端子，所述第二端子被配置为传送整流的 电压。