公开(公告)号：US20240070064A1

公开(公告)日：2024-02-29

申请号：US17893342

申请日：2022-08-23

Applicant: Arm Limited

Inventor： Richard Jared COOPER

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F2212/7201

Abstract: Circuitry comprises memory address translation circuitry to access memory circuitry storing translation information defining memory address translations from input memory addresses to respective output memory addresses; in which the translation information stored by the memory circuitry comprises a hierarchy of page table levels from a highest page table level to a lowest page table level, each page table level having one or more level tables each comprising two or more entries, in which an entry of a level table at a page table level other than a last page table level of the hierarchy points to a level table at a next lower page table level in the hierarchy; the memory address translation circuitry being configured to select an entry of a level table at each page table level according to a selection value, the selection value being dependent upon a portion, applicable to that page table level, of a given input memory address; in which the memory circuitry is configured to store entries as groups of entries, a group of entries being accessible by a single memory retrieval operation; and in which, for at least a subset of the page table levels, a group of entries stored by the memory circuitry comprises a set of entries from two or more respective level tables.

公开(公告)号：US11914522B2

公开(公告)日：2024-02-27

申请号：US17907206

申请日：2021-02-08

Applicant: ARM LIMITED

Inventor： Jason Parker

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/14

CPC classification number: G06F12/10 ,  G06F12/1027 ,  G06F12/14 ,  G06F2212/1032

Abstract: Apparatuses, methods, and programs for performing a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed are disclosed. A page table descriptor is accessed when performing the translation, which comprises translation parameters for the translation. The descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters.

公开(公告)号：US20240061613A1

公开(公告)日：2024-02-22

申请号：US17890456

申请日：2022-08-18

Applicant: Arm Limited

Inventor： Pavel SHAMIS ,  Honnappa NAGARAHALLI ,  Jamshed JALAL

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0635 ,  G06F3/0673 ,  G06F3/0604

Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.

公开(公告)号：US11907723B2

公开(公告)日：2024-02-20

申请号：US17699326

申请日：2022-03-21

Applicant: Arm Limited

Inventor： Nicholas Andrew Plante ,  Joseph Michael Pusdesris ,  Jungsoo Kim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/30029 ,  G06F9/30079 ,  G06F9/30181

Abstract: A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result.

公开(公告)号：US11907301B2

公开(公告)日：2024-02-20

申请号：US17260109

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt ,  François Christopher Jacques Botman

IPC: G06F16/903 ,  G06F12/1009 ,  G06F12/14

CPC classification number: G06F16/90339 ,  G06F12/1009 ,  G06F12/1483 ,  G06F16/90348

Abstract: A control table (22) defines information for controlling a processing component (20) to perform an operation. The table (22) comprises entries each corresponding to a variable size region defined by a first limit address and one of a second limit address and size. A binary search procedure is provided for looking up the table, comprising a number of search window narrowing steps, each narrowing a current search window of candidate entries to a narrower search window comprising fewer entries, based on a comparison of a query address against the first limit address of a selected candidate entry of the current search window. The comparison is independent of the second limit address or size of the selected candidate entry. After the search window is narrowed to a single entry, the query address is compared with the second limit address or size of that single entry.

公开(公告)号：US20240055035A1

公开(公告)日：2024-02-15

申请号：US17885753

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, JR.

IPC: G11C8/08 ,  G11C8/10

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: Dynamic power management for an on-chip memory, such as a system cache memory as well as other memories, is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section.

公开(公告)号：US20240054065A1

公开(公告)日：2024-02-15

申请号：US17887927

申请日：2022-08-15

Applicant: Arm Limited

Inventor： Brendan James Moran ,  Hugo John Martin Vincent ,  Michael Bartling

IPC: G06F11/34 ,  G06K9/62

CPC classification number: G06F11/3495 ,  G06K9/6262

Abstract: A behavioral sensor for creating consumable events can include: a feature extractor coupled to receive an event stream of events performed by a circuit, wherein the feature extractor identifies features of a particular event of the event stream and associates the particular event with a time; and a classifier coupled to receive the features of the particular event from the feature extractor, wherein the classifier classifies the particular event into a classified event associated with the time using predefined categories based on the received features of the particular event; whereby the classified event and subsequent classified events extracted from the event stream within a time frame are appended in a time series forming the consumable events.

公开(公告)号：US11900995B2

公开(公告)日：2024-02-13

申请号：US17223950

申请日：2021-04-06

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Ayush Kulshrestha ,  Munish Kumar

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

公开(公告)号：US11900522B2

公开(公告)日：2024-02-13

申请号：US17821666

申请日：2022-08-23

Applicant: Arm Limited

Inventor： Isidoros Sideris ,  Péter Sonkoly ,  Adrian Pereiro Castro

IPC: G06T15/00 ,  G06F9/38

CPC classification number: G06T15/005 ,  G06F9/3887

Abstract: Disclosed is a method of handling thread termination events within a graphics processor when a group of plural execution lanes are executing in a co-operative state. When a group of lanes is in the co-operative state, in response to the graphics processor encountering an event that means that a subset of one or more execution threads associated with the group of execution lanes in the co-operative state should be terminated: it is determined whether a condition to immediately terminate the subset of one or more execution threads is met. When the condition is not met, the group of execution lanes continue their execution in the co-operative state, but a record is stored to track that the threads in the subset of one or more execution threads should subsequently be terminated.

公开(公告)号：US20240046065A1

公开(公告)日：2024-02-08

申请号：US17817142

申请日：2022-08-03

Applicant: Arm Limited

Inventor： Hokchhay Tann ,  Ramon Matas Navarro ,  Igor Fedorov ,  Chuteng Zhou ,  Paul Nicholas Whatmough ,  Matthew Mattina

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to determine options for decisions in connection with design features of a computing device. In a particular implementation, design options for two or more design decisions of neural network processing device may be identified based, at least in part, on combination of a definition of available computing resources and one or more predefined performance constraints.