公开(公告)号：US07282404B2

公开(公告)日：2007-10-16

申请号：US10709829

申请日：2004-06-01

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

IPC: H01L21/8242

CPC classification number: H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

Abstract translation: 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

公开(公告)号：US07217981B2

公开(公告)日：2007-05-15

申请号：US10905473

申请日：2005-01-06

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Richard J. Rassel ,  Robert M Rassel

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Richard J. Rassel ,  Robert M Rassel

IPC: H01L21/004

CPC classification number: H01L28/20

Abstract: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

Abstract translation: 整合在集成电路中的可调TCR电阻和制造可调TCR电阻的方法。 可调TCR电阻器包括具有相反极性和不同幅度TCR，相同极性和不同幅度TCR或具有相反极性和大约相同TCR的两种或更多种不同材料的两个或更多个电阻器。

公开(公告)号：US07008852B2

公开(公告)日：2006-03-07

申请号：US11001140

申请日：2004-12-02

Applicant: Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

Inventor： Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract translation: 一种在半导体材料的两个区域之间形成至少一个界面区域的方法。 在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

公开(公告)号：US06992344B2

公开(公告)日：2006-01-31

申请号：US10319724

申请日：2002-12-13

Applicant: Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed ,  Richard P. Volant

Inventor： Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed ,  Richard P. Volant

IPC: H01L27/108

CPC classification number: H01L28/90 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02258 ,  H01L21/0228 ,  H01L21/31604 ,  H01L21/76807 ,  H01L21/76831 ,  H01L28/40 ,  H01L28/86

Abstract: The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

Abstract translation: 本发明涉及具有高k电介质层的独特的高表面积BEOL电容器结构及其制造方法。 这些高表面积BEOL电容器结构可用于模拟和混合信号应用。 电容器形成在具有沟槽内的基座的沟槽内，以提供额外的表面积。 顶部和底部电极使用大马士革集成方案创建。 电介质层被形成为多层电介质膜，该多层电介质膜包括例如Al 2 O 3 O 3，Al 2 O 3 O 3， / Ta 2 O 5，O 2 O 3 / Ta 2 O 2， 2/3/3/3等等。 电介质层可以通过诸如原子层沉积或化学气相沉积的方法沉积。 电容器中使用的电介质层也可以通过金属前体的阳极氧化产生高介电常数氧化物层。

公开(公告)号：US06891251B2

公开(公告)日：2005-05-10

申请号：US10323022

申请日：2002-12-18

Applicant: Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohammed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohammed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

IPC: H01L21/8222 ,  H01L27/08 ,  H01L29/93 ,  H01L29/94

CPC classification number: H01L27/0811 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract translation: 提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。 公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。 所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

公开(公告)号：US06878983B2

公开(公告)日：2005-04-12

申请号：US10728140

申请日：2003-12-04

Applicant: Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Mohamed Youssef Hammad ,  Jeffrey B. Johnson

Inventor： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Mohamed Youssef Hammad ,  Jeffrey B. Johnson

IPC: H01L27/08 ,  H01L29/93 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L29/93 ,  H01L27/0808 ,  Y10S438/979

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract translation: 一种变容二极管，具有在衬底中包括第一导电类型的阱区的第一电极，包括设置在所述阱区中的第二导电类型邻接隔离区的第一多个扩散区的第二电极和第二多个扩散 所述第一导电类型的区域从不邻近所述隔离区域的所述第一多个扩散区域的部分横向延伸并且具有大于所述第一多个扩散区域的掺杂剂浓度的掺杂剂浓度。 变容二极管在约0V至3V之间的施加电压范围内具有至少约3.5的可调谐性，约0V至2V之间的施加电压范围内的电容值的近似线性变化，以及至少约100的Q 大约2GHz的电路工作频率。

公开(公告)号：US06534371B2

公开(公告)日：2003-03-18

申请号：US09878605

申请日：2001-06-11

Applicant: Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

Inventor： Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

IPC: H01L21331

CPC classification number: H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

公开(公告)号：US06521506B1

公开(公告)日：2003-02-18

申请号：US10016539

申请日：2001-12-13

Applicant: Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohamed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohamed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

IPC: H01L2120

CPC classification number: H01L27/0811 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract translation: 提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。 公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。 所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

公开(公告)号：US06511873B2

公开(公告)日：2003-01-28

申请号：US09882749

申请日：2001-06-15

Applicant: Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh ,  Evgeni P. Gousev ,  Harald F. Okorn-Schmidt

Inventor： Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh ,  Evgeni P. Gousev ,  Harald F. Okorn-Schmidt

IPC: H01L2100

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

公开(公告)号：US06448124B1

公开(公告)日：2002-09-10

申请号：US09439067

申请日：1999-11-12

Applicant: Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

Inventor： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

IPC: H01L218238

CPC classification number: H01L21/76224 ,  H01L21/763 ,  H01L21/8249

Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

Abstract translation: 提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。