公开(公告)号：US11880065B2

公开(公告)日：2024-01-23

申请号：US17588470

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank ,  Takako Hirokawa

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/293

CPC classification number: G02B6/12007 ,  G02B6/13 ,  G02B6/29338

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes an edge coupler having a longitudinal axis, a first ring resonator, and a second ring resonator. The first ring resonator has a first center point that is spaced from the longitudinal axis of the edge coupler by a first perpendicular distance. The second ring resonator has a second center point that is spaced from the longitudinal axis of the edge coupler by a second perpendicular distance.

公开(公告)号：US20240022219A1

公开(公告)日：2024-01-18

申请号：US17864733

申请日：2022-07-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Paolo Valerio TESTA ,  Shafiullah SYED

IPC: H03F3/193 ,  H01L29/94

CPC classification number: H03F3/193 ,  H01L29/94 ,  H03F2200/451 ,  H03F2200/72

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a common-gate amplifier circuit and methods of operation. The structure includes at least one well in a substrate, a first metal layer connected to a gate of a transistor circuit, a second metal layer overlapped over the first metal layer to form a capacitor, and a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor. At least one capacitance in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.

公开(公告)号：US11876123B2

公开(公告)日：2024-01-16

申请号：US17214969

申请日：2021-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/737 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/732

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

公开(公告)号：US11869941B2

公开(公告)日：2024-01-09

申请号：US17679166

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sarah A. McTaggart ,  Rajendran Krishnasamy ,  Qizhi Liu

IPC: H01L21/265 ,  H01L29/732 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0817 ,  H01L21/26586 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

公开(公告)号：US20240006491A1

公开(公告)日：2024-01-04

申请号：US17852966

申请日：2022-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Qizhi LIU ,  Yves T. NGU ,  Ajay RAMAN ,  Rajendran KRISHNASAMY ,  Alvin J. JOSEPH

IPC: H01L29/10 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

公开(公告)号：US20240004140A1

公开(公告)日：2024-01-04

申请号：US17853186

申请日：2022-06-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B2006/12121

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core. The first waveguide core is positioned in a vertical direction between the second waveguide core and a substrate. The first waveguide core has a first longitudinal axis, the second waveguide core has a second longitudinal axis, and the second longitudinal axis of the second waveguide core is slanted at an angle relative to the first longitudinal axis of the first waveguide core.

公开(公告)号：US11862693B2

公开(公告)日：2024-01-02

申请号：US17000379

申请日：2020-08-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bong Woong Mun ,  Jeoung Mo Koo

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L29/401 ,  H01L29/402 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device may include a substrate having a source region and a drain region, and a gate arranged over the substrate and between the source region and the drain region. A first interlevel dielectric (ILD) layer may be at least partially arranged over the substrate and the gate. A conductive field plate may be arranged over the first ILD layer. At least one drain contact may extend through the first ILD layer over the drain region and may be coupled to the conductive field plate. A drain captive structure may be disposed in the first ILD layer and adjacent to the drain region, the drain captive structure having a trench comprising an air gap, wherein the drain captive structure is laterally spaced apart from sidewalls of the gate.

公开(公告)号：US11860414B2

公开(公告)日：2024-01-02

申请号：US17137549

申请日：2020-12-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Tymon Barwicz ,  Robert K. Leidy ,  Thomas Houghton

IPC: G02B6/26 ,  G02B6/42 ,  G02B6/10 ,  G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a waveguide core region on a first dielectric layer, and a second dielectric layer on the waveguide core region and the first dielectric layer. The waveguide core region has a tapered section with an end surface that terminates adjacent to an edge of the first dielectric layer. The second dielectric layer includes a first trench and a second trench that are each positioned adjacent to the tapered section of the waveguide core region.

公开(公告)号：US20230411384A1

公开(公告)日：2023-12-21

申请号：US17842266

申请日：2022-06-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya NATH ,  Robert J. GAUTHIER, JR. ,  Rajendran KRISHNASAMY

IPC: H01L27/02 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L27/0259 ,  H01L28/20

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge device (ESD) with a pinch resistor and methods of manufacture. The structure includes: a semiconductor substrate; a shallow trench isolation structure extending into the semiconductor substrate; an amorphous layer in the semiconductor substrate and below the shallow trench isolation structure; and a pinch resistor between the shallow trench isolation structure and the amorphous layer.

公开(公告)号：US11848374B2

公开(公告)日：2023-12-19

申请号：US17574785

申请日：2022-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson Holt

IPC: H01L29/737 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/737 ,  H01L21/76289 ,  H01L29/0649 ,  H01L29/66242

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.