公开(公告)号：US07518921B2

公开(公告)日：2009-04-14

申请号：US11688481

申请日：2007-03-20

申请人： Hiroshi Maejima ,  Makoto Hamada

发明人： Hiroshi Maejima ,  Makoto Hamada

IPC分类号： G11C16/04

CPC分类号： H01L27/0203 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a memory cell array, a word line, a source line, a row decoder, and a source line driver circuit. The memory cell array includes a memory cell unit having a plurality of memory cells connected in series. The word line is connected to control gates of the memory cells. The source line is electrically connected to sources of the memory cells positioned on one end sides of the memory cell unit. The row decoder selects the word line. The source line driver circuit is arranged in the row decoder and applies a first voltage to the source line.

摘要翻译： 半导体存储器件包括存储单元阵列，字线，源极线，行解码器和源极线驱动器电路。 存储单元阵列包括具有串联连接的多个存储单元的存储单元单元。 字线连接到存储器单元的控制栅极。 源极线电连接到位于存储单元单元的一端侧的存储单元的源极。 行解码器选择字线。 源极线驱动电路布置在行解码器中，并向源极线施加第一电压。

公开(公告)号：US07259990B2

公开(公告)日：2007-08-21

申请号：US11193456

申请日：2005-08-01

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A semiconductor memory device is disclosed, which includes a plurality of NAND cells each comprising a plurality of series-connected memory cell transistors, and a drain-side select transistor and a source-side select transistor connected to a drain-side end and a source-side end of the series-connected memory cell transistors, respectively, a source line commonly connected to the source-side select transistors in the plurality of NAND cells, a first discharge circuit which is connected between the source line and a reference potential and whose conduction/non-conduction is controlled by a first control signal, and a second discharge circuit which is connected between the source line and the reference potential and whose conduction/non-conduction is controlled by a second control signal different from the first control signal.

摘要翻译： 公开了一种半导体存储器件，其包括多个NAND单元，每个NAND单元包括多个串联存储单元晶体管，漏极侧选择晶体管和源极侧选择晶体管连接到漏极侧端和源极 串联的存储单元晶体管的端部分别是与多个NAND单元中的源极侧选择晶体管共同连接的源极线，连接在源极线和参考电位之间的第一放电电路， 导通/非导通由第一控制信号控制，第二放电电路连接在源极线和参考电位之间，其导通/非导通由与第一控制信号不同的第二控制信号控制。

公开(公告)号：US20060250848A1

公开(公告)日：2006-11-09

申请号：US11402980

申请日：2006-04-13

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： According to one embodiment of this invention, a non-volatile semiconductor memory device of high speed program operation is realized. It provides a non-volatile semiconductor memory device comprising a cell array in which NAND strings having electrically re-programmable memory cells are connected in series are disposed in a matrix form; sense amplifiers for sensing threshold voltages of said memory cells by sensing potentials of bitlines connected to said memory cells and for having a first region having high voltage transistors and a second region having low voltage transistors; cell source lines connected to an end of said NAND strings; and a first cell source line driver being connected to said cell source lines and having a first transistor for supplying a grounding potential or a low potential to said cell source line, said first transistor of said cell source line driver being disposed in said first region of said sense amplifiers.

摘要翻译： 根据本发明的一个实施例，实现了高速程序操作的非易失性半导体存储器件。 它提供了一种包括单元阵列的非易失性半导体存储器件，其中具有电可重新编程的存储器单元的NAND串串联连接，其中矩阵形式; 感测放大器，用于通过感测连接到所述存储器单元的位线的电位并且具有具有高电压晶体管的第一区域和具有低电压晶体管的第二区域来感测所述存储器单元的阈值电压; 连接到所述NAND串的一端的单元源极线; 以及第一单元源极线驱动器，其连接到所述单元源极线，并具有用于向所述单元源极线提供接地电位或低电位的第一晶体管，所述单元源极线驱动器的所述第一晶体管设置在 所述感测放大器。

公开(公告)号：US20060140013A1

公开(公告)日：2006-06-29

申请号：US11245195

申请日：2005-10-07

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/24

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/26

摘要： A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit line control circuit comprises a first transistor and a second transistor with a breakdown voltage higher than that of the first transistor, the second transistor being disposed between the first transistor and a bit line in the memory cell array to be serially connected to the first transistor, and wherein a connection node between the first and second transistors is fixed in potential at a data erase time.

公开(公告)号：US06639848B2

公开(公告)日：2003-10-28

申请号：US10198079

申请日：2002-07-19

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C1604

CPC分类号： G11C29/789 ,  G11C29/44 ,  G11C2029/2602

摘要： A semiconductor memory device is provided which can apply a redundancy circuit replacement program to cells by a DS testing in a parallel testing state. That is, in this semiconductor memory device, when the redundancy circuit replacement is effected on an electrically programmable nonvolatile memory device, an internal circuit is so provided as to detect a defect chip retrievable on a DS tester while being in a parallel testing state as well as address information contained in the defect chip and, by doing so, it is possible to achieve the redundancy circuit replacement.

公开(公告)号：US4271513A

公开(公告)日：1981-06-02

申请号：US37383

申请日：1979-05-09

申请人： Hiroshi Maejima ,  Noriaki Fujimura ,  Takahiro Shibuya ,  Shigeyuki Akagi

发明人： Hiroshi Maejima ,  Noriaki Fujimura ,  Takahiro Shibuya ,  Shigeyuki Akagi

IPC分类号： G06F11/22 ,  G06F13/00 ,  H04B17/40 ,  H04L1/24 ,  H04L5/22 ,  H04L29/14 ,  G06F11/00

CPC分类号： H04L1/24 ,  H04B17/406

摘要： The present invention discloses a method for carrying out a loopback test in a data communication system having a first data communication station, a second data communication station and a transmission line connected therebetween. The first data communication station transmits a succession of a first pseudo-random noise signal, a loopback test signal and a second pseudo-random noise signal to the second data communication station by utilizing a usual information data channel, and requires no special channel for carrying out the loopback test. When the second data communication station detects the first pseudo-random noise signal, it transmits the loopback test signal to the first data communication station in order to check the coincidence of the transmitted and the received loopback test signals. The second pseudo-random noise signal denotes the end of the loopback test.

摘要翻译： 本发明公开了一种在具有连接在其间的第一数据通信站，第二数据通信站和传输线的数据通信系统中进行环回测试的方法。 第一数据通信站通过利用通常的信息数据信道将第一伪随机噪声信号，环回测试信号和第二伪随机噪声信号的序列发送到第二数据通信站，并且不需要用于承载的特殊信道 进行环回测试。 当第二数据通信站检测到第一伪随机噪声信号时，它将环回测试信号发送到第一数据通信站，以便检查所发送的和所接收的环回测试信号的一致性。 第二伪随机噪声信号表示环回测试的结束。

公开(公告)号：US08820736B2

公开(公告)日：2014-09-02

申请号：US13755624

申请日：2013-01-31

申请人： Hiroshi Maejima ,  Hiroto Akiyama

发明人： Hiroshi Maejima ,  Hiroto Akiyama

IPC分类号： B65H31/36 ,  B65H31/00 ,  B65H31/38 ,  B65H31/30 ,  B65H31/10 ,  B65H29/34 ,  B65H31/34 ,  B65H29/14 ,  B65H31/20

CPC分类号： B65H29/14 ,  B65H9/101 ,  B65H29/34 ,  B65H31/10 ,  B65H31/20 ,  B65H31/3027 ,  B65H31/34 ,  B65H31/38 ,  B65H2301/4212 ,  B65H2301/4213 ,  B65H2403/411 ,  B65H2404/1521 ,  B65H2404/1523 ,  B65H2404/166 ,  B65H2404/232 ,  B65H2404/242 ,  B65H2404/731 ,  B65H2404/742 ,  B65H2553/612 ,  B65H2553/83 ,  B65H2801/27

摘要： To provide a post-processing apparatus for preventing a sheet from becoming misaligned in dropping the rear end side of the sheet carried in a processing tray from a sheet discharge path to store on the tray, and enabling the mechanism to be simplified, compact and configured at low cost, a sheet guide that guides a sheet from the sheet discharge path to the processing tray is comprised of a pair of right and left guide members, at the same time in the processing tray are disposed a pair of right and left side edge alignment members, and each guide member and each side edge alignment member are configured to shift to positions in the sheet width direction in an integral manner using a common drive motor.

摘要翻译： 为了提供一种后处理装置，用于防止片材在从处理托盘中携带的片材的后端侧从片材排出路径落下而不能对准以存储在托盘上，并且使得该机构能够被简化，紧凑和配置 以低成本，将片材从片材排出路径引导到处理托盘的片材引导件由一对左右引导构件构成，并且在处理托盘中同时设置有一对左右侧边缘 对准构件，并且每个引导构件和每个侧边对准构件被构造成使用公共驱动马达以一体的方式移动到片材宽度方向上的位置。

公开(公告)号：US08693250B2

公开(公告)日：2014-04-08

申请号：US13460134

申请日：2012-04-30

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C16/04

CPC分类号： H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.

摘要翻译： 根据本发明的示例的三维堆叠的非易失性半导体存储器包括由并排布置的第一和第二块以及设置在第一和第二块之间的驱动器组成的存储单元阵列。 至少两个具有与第一和第二块中的至少两个导电层相同结构的导电层设置在驱动器上，并且第一和第二块中的选择栅极线通过至少两个连接到驱动器 驱动器上的导电层。

公开(公告)号：US08625329B2

公开(公告)日：2014-01-07

申请号：US13187891

申请日：2011-07-21

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0083

摘要： A semiconductor memory device includes: a memory cell array including multiple first lines, multiple second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and including variable resistive elements; and a control circuit which controls resistance values of the variable resistive elements in a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected first line and a selected second line by applying first and second voltages to the selected first and second lines, respectively. The control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and a pulsing voltage as the second voltage to the selected second line.

摘要翻译： 半导体存储器件包括：存储单元阵列，包括多个第一线，与第一线交叉的多个第二线，以及布置在第一线和第二线之间的交叉点处并包括可变电阻元件的存储单元; 以及控制电路，其以将单元电压施加到布置在所选择的第一线路和所选择的第二线路之间的交叉点处的存储器单元的方式来控制可变电阻元件的电阻值，所述方法是将第一和第二电压施加到所选择的第一 和第二行。 控制电路将从第一初始电压逐渐升高或降低的电压作为第一电压施加到所选择的第一线，并且将脉冲电压作为第二电压施加到所选择的第二线。

公开(公告)号：US08605506B2

公开(公告)日：2013-12-10

申请号：US13693449

申请日：2012-12-04

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.