公开(公告)号：US10200294B2

公开(公告)日：2019-02-05

申请号：US15387718

申请日：2016-12-22

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Alex Shpiner ,  Vladimir Zdornov ,  Zachy Haramaty ,  Eitan Zahavi

IPC: H04L12/28 ,  H04Q11/00 ,  H04L12/801 ,  H04L12/707

Abstract: A method for network communication includes receiving in a network element a packet for forwarding to a destination node. The destination node is reachable via two or more candidate ports of the network element that are connected to respective next-hop network elements. Link-level flow-control credit notifications are received in the network element from the next-hop network elements via the respective candidate ports. An egress port is selected for the packet, from among the candidate ports, based at least on the received link-level flow-control credit notifications. The packet is forwarded toward the destination node over the selected egress port.

公开(公告)号：US20190036821A1

公开(公告)日：2019-01-31

申请号：US15663758

申请日：2017-07-30

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Gil Levy ,  Pedro Reviriego ,  Aviv Kfir ,  Salvatore Pontarelli

IPC: H04L12/747 ,  G06F12/0868 ,  H04L12/743

Abstract: Communication apparatus includes a TCAM, which stores a corpus of rules, including respective sets of unmasked and masked bits. The rules conform to respective rule patterns, each defining a different, respective sequence of masked and unmasked bits to which one or more of the rules conform. A RAM caches rule entries corresponding to rules belonging to one or more of the rule patterns that have been selected for caching. Decision logic extracts respective classification keys from data packets, each key including a string of bits extracted from selected fields in a given data packet, and classifies the data packets by first matching the respective classification keys to the cached rule entries in the RAM and, when no match is found in the RAM, by matching the respective classification keys to the rules in the TCAM.

公开(公告)号：US10148571B2

公开(公告)日：2018-12-04

申请号：US15186562

申请日：2016-06-20

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Pedro Reviriego ,  Salvatore Pontarelli ,  Gil Levy

IPC: H04L12/745 ,  H04L12/753

Abstract: A routing table is represented as a binary search tree ordered by prefix lengths. Markers are placed to guide accessing nodes in designated subtrees to search for a longest prefix match with destination addresses of data packet. Destination descendant nodes in remote hierarchical levels of the tree are associated with the markers. The traversal of the binary search tree is conducted by accessing the respective destination descendant nodes while avoiding accessing nodes in intermediate hierarchical levels. The packet is processed using the longest prefix match.

公开(公告)号：US20180343613A1

公开(公告)日：2018-11-29

申请号：US15607494

申请日：2017-05-28

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Lavi Koch

IPC: H04W52/02 ,  G06F1/32

CPC classification number: H04W52/0222 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  H04W52/0206

Abstract: A network element includes circuitry and multiple ports. The ports are configured to transmit packets to a common destination via multiple paths of a communication network. Each port includes multiple serializers that serially transmit the packets over respective physical lanes. The power consumed by each port is a nonlinear function of the number of serializers activated in the port. The circuitry is configured to select one or more serializers among the ports to (i) meet a throughput demand via the ports and (ii) minimize an overall power consumed by the ports under a constraint of the nonlinear function, and to activate only the selected serializers. The circuitry is configured to choose for a packet received in the network element and destined to the common destination a port in which at least one of the serializers is activated, and to transmit the packet to the common destination via the chosen port.

公开(公告)号：US20180199292A1

公开(公告)日：2018-07-12

申请号：US15401042

申请日：2017-01-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Liron Mula ,  Lavi Koch ,  Gil Levy ,  Aviv Kfir ,  Benny Koren

IPC: H04W52/24 ,  H04W72/04 ,  H04L12/44

CPC classification number: H04L12/44 ,  G06F1/325

Abstract: Power consumption is controlled in a fabric of interconnected network switches in which there are queues for data awaiting transmission through the fabric and a plurality of lanes for carrying the data between ports of the switches, A bandwidth manager iteratively determines current queue byte sizes, and assigns respective bandwidths to the switches according to the current queue byte sizes. Responsively to the assigned bandwidths, the bandwidth manager causes a portion of the lanes of the switches to be disabled so as to maintain a power consumption of the fabric below a predefined limit.

公开(公告)号：US20180145881A1

公开(公告)日：2018-05-24

申请号：US15814430

申请日：2017-11-16

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Vladimir Zdornov ,  Eitan Zahavi

IPC: H04L12/24 ,  H04L12/751 ,  H04L29/12

CPC classification number: H04L41/12 ,  H04L41/0853 ,  H04L45/02 ,  H04L47/621 ,  H04L61/2038 ,  H04L61/609

Abstract: An apparatus includes a network interface and a processor. The network interface is configured to communicate with a network that includes a plurality of switches interconnected in a Cartesian topology having a number D of dimensions. The processor is configured to hold, in a memory, a grid representation of the Cartesian topology, the grid representation including grid points associated respectively with the plurality of switches, to traverse the grid points and assign D-dimensional coordinates to the respective switches, and based on the assigned coordinates, to configure at least some of the switches with routing information via the network interface.

公开(公告)号：US20180006921A1

公开(公告)日：2018-01-04

申请号：US15492003

申请日：2017-04-20

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： David Mozes ,  Liron Mula ,  Benny Koren

IPC: H04L12/26 ,  H04L12/875 ,  H04L29/06

CPC classification number: H04L47/56 ,  H04L43/028 ,  H04L43/0876 ,  H04L49/50 ,  H04L63/00 ,  H04L63/0254 ,  H04L63/101 ,  H04L69/22

Abstract: A network switch includes circuitry, multiple ports and multiple hardware-implemented distinct-flow counters. The multiple ports are configured to receive packets from a communication network. Each of the multiple hardware-implemented distinct-flow counters is configured to receive (i) a respective count definition specifying one or more packet-header fields and (ii) a respective subset of the received packets, and to estimate a respective number of distinct flows that are present in the subset, by evaluating, over the packets in the subset, a number of distinct values in the packet-header fields belonging to the count definition. The circuitry is configured to provide each of the distinct-flow counters with the respective subset of the received packets, including providing a given packet to a plurality of the distinct-flow counters, and to identify an event-of-interest based on numbers of distinct flows estimated by the distinct-flow counters.

公开(公告)号：US20170373989A1

公开(公告)日：2017-12-28

申请号：US15194585

申请日：2016-06-28

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Barak Gafni ,  Benny Koren ,  George Elias ,  Itamar Rabenstein ,  Eyal Srebro ,  Sagi Kuks ,  Niv Aibester

IPC: H04L12/947 ,  H04L12/801 ,  H04L12/851 ,  H04L12/863

CPC classification number: H04L49/25 ,  H04L47/12 ,  H04L47/24 ,  H04L47/245 ,  H04L47/6295 ,  H04L49/253

Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is zero are assigned to a first group, while the flows for which the respective number is non-zero are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.

公开(公告)号：US09853900B1

公开(公告)日：2017-12-26

申请号：US15670055

申请日：2017-08-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Liron Mula ,  Gil Levy ,  Aviv Kfir

IPC: H04L12/28 ,  H04L12/803 ,  H04L12/707 ,  H04L12/709 ,  H04L12/24 ,  H04L12/743

CPC classification number: H04L47/125 ,  H04L41/0893 ,  H04L45/24 ,  H04L45/245 ,  H04L45/7453

Abstract: ECMP routing is carried out in fabric of network entities by representing valid destinations and invalid destinations in a group of the entities by a member vector. The order of the elements in the member vector is permuted and fanned out. A portion of the elements in the fanned out vector is pseudo-randomly masked. A flow of packets is transmitted to the first valid destination in the masked member vector.

公开(公告)号：US20170286292A1

公开(公告)日：2017-10-05

申请号：US15086095

申请日：2016-03-31

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Salvatore Pontarelli ,  Pedro Reviriego

IPC: G06F12/02 ,  G06F12/04

CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/04 ,  G06F17/3033 ,  H04L45/7453 ,  H04L45/7457

Abstract: In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.