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    LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH MULTIPLE PROCESSOR CORES
    121.
    发明申请
    LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH MULTIPLE PROCESSOR CORES 有权

    公开(公告)号：US20230044581A1

    公开(公告)日：2023-02-09

    申请号：US17394714

    申请日：2021-08-05

    Applicant: Xilinx, Inc.

    Inventor： Tim Tuan ,  Seokjoong Kim ,  Sai Anirudh Jayanthi

    IPC: G06F30/20 ,  G06F1/06 ,  G06F1/28 ,  G06F12/02

    Abstract: Learning-based power modeling of a processor core includes generating, using computer hardware, pipeline snapshot data specifying a plurality of snapshots for a pipeline of a processor core. Each snapshot specifies a state of the pipeline for a clock cycle in executing a computer program over a plurality of clock cycles. A plurality of estimates of power consumption for the processor core in executing the computer program for the plurality of clock cycles are determined, using an instruction-based power model executed by the computer hardware, a based on the pipeline snapshot data. The plurality of estimates of power consumption are calculated using the instruction-based power model based on the plurality of snapshots over the plurality of clock cycles.

    DYNAMICALLY ALLOCATED BUFFER POOLING
    122.
    发明申请
    DYNAMICALLY ALLOCATED BUFFER POOLING 有权

    公开(公告)号：US20230036531A1

    公开(公告)日：2023-02-02

    申请号：US17389272

    申请日：2021-07-29

    Applicant: XILINX, INC.

    Inventor： Krishnan SRINIVASAN ,  Shishir KUMAR ,  Sagheer AHMAD ,  Abbas MORSHED ,  Aman GUPTA

    IPC: G06F3/06

    Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

    Neural network processing system having host controlled kernel acclerators
    123.
    发明授权
    Neural network processing system having host controlled kernel acclerators 有权

    公开(公告)号：US11568218B2

    公开(公告)日：2023-01-31

    申请号：US15786288

    申请日：2017-10-17

    Applicant: Xilinx, Inc.

    Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Ashish Sirasao

    IPC: G06N3/063 ,  G06N3/04

    Abstract: A disclosed neural network processing system includes a host computer system, a RAMs coupled to the host computer system, and neural network accelerators coupled to the RAMs, respectively. The host computer system is configured with software that when executed causes the host computer system to write input data and work requests to the RAMS. Each work request specifies a subset of neural network operations to perform and memory locations in a RAM of the input data and parameters. A graph of dependencies among neural network operations is built and additional dependencies added. The operations are partitioned into coarse grain tasks and fine grain subtasks for optimal scheduling for parallel execution. The subtasks are scheduled to accelerator kernels of matching capabilities. Each neural network accelerator is configured to read a work request from the respective RAM and perform the subset of neural network operations on the input data using the parameters.

    SHARED MULTI-PORT MEMORY FROM SINGLE PORT
    124.
    发明申请
    SHARED MULTI-PORT MEMORY FROM SINGLE PORT 有权

    公开(公告)号：US20230023866A1

    公开(公告)日：2023-01-26

    申请号：US17750297

    申请日：2022-05-20

    Applicant: XILINX, INC.

    Inventor： Richard Lewis WALKE ,  John Edward MCGRATH

    IPC: G11C7/10 ,  G11C8/16

    Abstract: Embodiments herein describe a multi-port memory system that includes one or more single port memories (e.g., a memory that can perform only one read or one write at any given time, referred to as a 1W or 1R memory). That is, the multi-port memory system can perform multiple read and writes in parallel (e.g., 1R/1W, 1R/3W, 2R/2W, 3R/1W, etc.) even though the memory in the system can only perform one read or one write at any given time. The advantage of doing so is a reduction in area and power.

    Logical transport overlayed over a physical transport having a tree topology
    125.
    发明授权
    Logical transport overlayed over a physical transport having a tree topology 有权

    公开(公告)号：US11563639B1

    公开(公告)日：2023-01-24

    申请号：US16025762

    申请日：2018-07-02

    Applicant: Xilinx, Inc.

    Inventor： Millind Mittal ,  Jaideep Dastidar

    IPC: H04L41/12 ,  H04L41/0803

    Abstract: In an example, a system specifies a first configuration of the physical transport network that models a plurality of devices as a corresponding first plurality of nodes having a tree topology. Each node of the first plurality of nodes has at least one first device identifier and at least one first connection identifier to other nodes in the tree topology. The system specifies a second configuration of the logical transport network that models the plurality of devices as the first plurality of nodes having a non-tree topology. Each node of the first plurality of nodes has at least one second device identifier, at least one second connection identifier to other nodes in the non-tree topology, the at least one first device identifier, and the at least one first connection identifier of the tree topology. The system folds the logical transport network over the physical transport network using the at least one second device identifier, at least one second connection identifier to other nodes in the non-tree topology, the at least one first device identifier, and the at least one first connection identifier of the tree topology.

    Hierarchical access simulation for signaling with more than two state values
    126.
    发明授权
    Hierarchical access simulation for signaling with more than two state values 有权

    公开(公告)号：US11543452B1

    公开(公告)日：2023-01-03

    申请号：US17014128

    申请日：2020-09-08

    Applicant: Xilinx, Inc.

    Inventor： Saikat Bandyopadhyay ,  Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Ender Tunc Eroglu ,  Rupendra Bakoliya ,  Jayashree Rangarajan

    IPC: G06F11/00 ,  G01R31/3183 ,  G06F30/3308

    Abstract: A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

    COMPUTE DATAFLOW ARCHITECTURE
    128.
    发明申请
    COMPUTE DATAFLOW ARCHITECTURE 有权

    公开(公告)号：US20220368330A1

    公开(公告)日：2022-11-17

    申请号：US17876456

    申请日：2022-07-28

    Applicant: XILINX, INC.

    Inventor： Steven P. YOUNG ,  Brian C. GAIDE

    IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

    Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

    Tiling control circuit for downloading and processing an input tile based on source and destination buffer availability
    129.
    发明授权
    Tiling control circuit for downloading and processing an input tile based on source and destination buffer availability 有权

    公开(公告)号：US11501142B1

    公开(公告)日：2022-11-15

    申请号：US16374451

    申请日：2019-04-03

    Applicant: Xilinx, Inc.

    Inventor： Victor J. Wu ,  Poching Sun ,  Thomas A. Branca ,  Justin Thant Hsin Oo

    IPC: G06N3/063 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

    Abstract: A download dispatch circuit initiates download of an input tile of an input feature map in response to a source buffer of two or more source buffers being available for the input tile, and indicates that the input tile is available in response to completion of the download. An operation dispatch circuit initiates a neural network operation on the input tile in response to the input tile being available and a first destination buffer of two or more destination buffers being available for an output tile of an output feature map, and indicates that the output tile is available in response to completion of the neural network operation. An upload dispatch circuit initiates upload of the output tile to the output feature map in response to the output tile being available, and indicates that the first destination buffer is available in response to completion of the upload.

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