公开(公告)号：US09135139B2

公开(公告)日：2015-09-15

申请号：US13535334

申请日：2012-06-27

Applicant: Youfeng Wu ,  Justin E. Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano L. Pereira

Inventor： Youfeng Wu ,  Justin E. Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano L. Pereira

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/00 ,  G06F9/45 ,  G06F3/00 ,  G06F9/46 ,  G06F13/00 ,  G06F11/36

CPC classification number: G06F11/3688 ,  G06F8/70 ,  G06F11/36 ,  G06F11/3632

Abstract: Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

Abstract translation: 公开了在多线程程序中识别和再现并发错误的方法和系统。 本文公开的示例性方法包括定义数据类型。 数据类型包括与第一条件相关联的多线程程序的第一线程相关联的第一谓词，与多线程程序的第二线程相关联的第二谓词，第二谓词与第一谓词相关联 第二个条件和一个定义第一个谓词和第二个谓词之间的关系的表达式。 这种关系在满足时会导致并发错误被检测到。 符合数据类型的并发错误检测器用于检测多线程程序中的并发错误。

公开(公告)号：US09117021B2

公开(公告)日：2015-08-25

申请号：US13827121

申请日：2013-03-14

Applicant: Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

Inventor： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

IPC: G06F11/36

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

Abstract translation: 公开了方法，装置，系统和制品以管理并发谓词表达。 一种示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。

公开(公告)号：US08954775B2

公开(公告)日：2015-02-10

申请号：US13528548

申请日：2012-06-20

Applicant: Jaewoong Chung ,  Hanjun Kim ,  Youfeng Wu

Inventor： Jaewoong Chung ,  Hanjun Kim ,  Youfeng Wu

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/30083 ,  G06F9/3836 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有核心的装置，其核心包括各自执行目标指令集架构（ISA）的指令的功能单元和功率控制器，以响应于功率识别领域来控制第一功能单元的功率模式 要在核心上执行的代码块的功率区域的功率指令。 描述和要求保护其他实施例。

公开(公告)号：US08935678B2

公开(公告)日：2015-01-13

申请号：US13442703

申请日：2012-04-09

Applicant: Youfeng Wu ,  Cheng Wang ,  Ho-Seop Kim

Inventor： Youfeng Wu ,  Cheng Wang ,  Ho-Seop Kim

IPC: G06F9/45 ,  G06F11/28 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F11/28 ,  G06F8/52 ,  G06F9/30087 ,  G06F9/45516

Abstract: Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.

Abstract translation: 提供了形成弹性目标指令结构的方法和装置。 示例性方法通过编译一个或多个弹性事务来获得源指令结构并形成弹性目标指令结构。

公开(公告)号：US20140282423A1

公开(公告)日：2014-09-18

申请号：US13827121

申请日：2013-03-14

Applicant: Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

Inventor： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

IPC: G06F11/36

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

Abstract translation: 公开了方法，装置，系统和制品以管理并发谓词表达。 一种示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。

公开(公告)号：US20140281246A1

公开(公告)日：2014-09-18

申请号：US13836374

申请日：2013-03-15

Applicant: Mauricio Breternitz, JR. ,  Youfeng Wu ,  Peter Sassone ,  James Mason ,  Aashish Phansalkar ,  Balaji Vijayan

Inventor： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Peter Sassone ,  James Mason ,  Aashish Phansalkar ,  Balaji Vijayan

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/30 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3842 ,  G06F12/0886

Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

Abstract translation: 公开了一种以高精度预测并保留先前执行的指令的指令边界以便解码可变长度指令的系统，处理器和方法。 在至少一个实施例中，所公开的处理器包括指令提取单元，指令高速缓存，边界字节预测器和指令解码器。 在一些实施例中，指令获取单元提供指令地址，并且指令高速缓冲存储器产生与指令地址对应的指令标签和指令高速缓存内容。 在一些实施例中，指令解码器包括用于确定指令高速缓存内容中的指令边界的边界字节逻辑。

公开(公告)号：US20140095778A1

公开(公告)日：2014-04-03

申请号：US13630651

申请日：2012-09-28

Applicant: Jaewoong Chung ,  Youfeng Wu ,  Cheng Wang

Inventor： Jaewoong Chung ,  Youfeng Wu ,  Cheng Wang

IPC: G06F12/00

CPC classification number: G06F12/0888 ,  G06F9/4552 ,  G06F12/0246 ,  G06F12/0897 ,  G06F2212/452

Abstract: Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.

Abstract translation: 公开了在非易失性存储器中缓存代码的方法和装置。 所公开的示例性方法包括识别第一代码的代码请求的实例，识别第一代码是否存储在非易失性（NV）随机存取存储器（RAM）高速缓存上，以及当NV RAM缓存中不存在第一代码时 当与第一代码相关联的第一条件被满足时，将第一代码添加到NV RAM高速缓存，并且当不满足第一条件时防止将第一代码存储到NV RAM高速缓存。

公开(公告)号：US08683243B2

公开(公告)日：2014-03-25

申请号：US13046031

申请日：2011-03-11

Applicant: Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US20130283014A1

公开(公告)日：2013-10-24

申请号：US13996610

申请日：2011-09-27

Applicant: Cheng Wang ,  Youfeng Wu

Inventor： Cheng Wang ,  Youfeng Wu

IPC: G06F9/30

CPC classification number: G06F9/30098 ,  G06F8/434 ,  G06F8/4441 ,  G06F9/3834 ,  G06F9/45516

Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for expediting execution time memory alias checking. A sequence of instructions targeted for execution on an execution processor may be received or retrieved. The execution processor may include a plurality of alias registers and circuitry configured to check entries in the alias register for memory aliasing. One or more optimizations may be performed on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions. This may include a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions. After the optimization, one or more move instructions may be inserted in the optimized sequence of instructions to move one or more entries among the alias registers during execution, to expedite alias checking at execution time. Other embodiments may be described and/or claimed.

Abstract translation: 本文描述了装置，计算机实现的方法，系统和计算机可读介质的实施例，用于加速执行时间存储器别名检查。 可以接收或检索针对执行处理器执行的指令序列。 执行处理器可以包括多个别名寄存器和被配置为检查别名寄存器中的条目以用于存储器混叠的电路。 可以对所接收或检索的指令序列执行一个或多个优化，以优化所接收或检索的指令序列的执行性能。 这可以包括在接收或检索的指令序列中的多个存储器指令的重排序。 在优化之后，可以在优化的指令序列中插入一个或多个移动指令以在执行期间移动别名寄存器中的一个或多个条目，以在执行时加速别名检查。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130275700A1

公开(公告)日：2013-10-17

申请号：US13995943

申请日：2011-09-29

Applicant: Cheng Wang ,  Youfeng Wu ,  Jaewoong Chung

Inventor： Cheng Wang ,  Youfeng Wu ,  Jaewoong Chung

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

Abstract: Embodiments of the present disclosure describe a processor, which may include copy circuitry coupled to a shadow register file and a control register. The copy circuitry may be configured to copy content from a range of a number of registers to a shadow range of the shadow register file in a forward or backward direction. The forward or backward direction may be based at least in part on a value stored in the control register.

Abstract translation: 本公开的实施例描述了一种处理器，其可以包括耦合到影子寄存器文件和控制寄存器的复制电路。 复制电路可以被配置为将内容从多个寄存器的范围向前或向后复制到影子寄存器文件的阴影范围。 前进或后退方向可以至少部分地基于存储在控制寄存器中的值。