公开(公告)号：US20090194799A1

公开(公告)日：2009-08-06

申请号：US12025618

申请日：2008-02-04

申请人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sakae Wada ,  Sheng Teng Hsu

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L27/14647 ,  H01L27/14689

摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.

摘要翻译： 提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。 两个独立像素用于三色检测。 第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。 两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。 底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。 顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。 单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

公开(公告)号：US07470946B2

公开(公告)日：2008-12-30

申请号：US11580407

申请日：2006-10-13

申请人： Sheng Teng Hsu ,  Jong-Jan Lee

发明人： Sheng Teng Hsu ,  Jong-Jan Lee

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14603 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14647 ,  H01L27/14683 ,  H01L27/14689

摘要： A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode set, and detects an independent output signal for each photodiode. Typically, the transistor set is formed in the top surface of the substrate. For example, the Si substrate may be a p-doped Si substrate, and the photodiode triple-junction structure includes the first photodiode forming a pn junction from an n+-doped region at the Si substrate top surface, to an underlying p-doped region. The second photodiode forms a pn junction from the p-doped region to an underlying n-well, and the third photodiode forms a pn junction from the n-well to the underlying p-doped Si substrate.

摘要翻译： 提供三结互补金属氧化物半导体（CMOS）无滤色器彩色成像器单元。 成像器单元由体硅（Si）衬底制成。 在Si衬底中形成包括第一，第二和第三光电二极管的光电二极管组作为三结结构。 晶体管组连接到光电二极管组，并检测每个光电二极管的独立输出信号。 通常，晶体管组形成在衬底的顶表面中。 例如，Si衬底可以是p掺杂的Si衬底，并且光电二极管三结结构包括第一光电二极管，其形成从Si衬底顶表面处的n +掺杂区域到下一个p掺杂区域的pn结 。 第二光电二极管形成从p掺杂区域到下面的n阱的pn结，并且第三光电二极管形成从n阱到下面的p掺杂Si衬底的pn结。

公开(公告)号：US07378286B2

公开(公告)日：2008-05-27

申请号：US10922712

申请日：2004-08-20

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Jong-Jan Lee

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Jong-Jan Lee

IPC分类号： H01L29/72

CPC分类号： H01L29/7869 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78621

摘要： The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2. The present invention ferroelectric transistor can be a metal-ferroelectric-semiconductive metal oxide FET having a gate stack of a top metal electrode disposed on a ferroelectric layer disposed on a semiconductive metal oxide channel on a substrate. Using additional layer of bottom electrode and gate dielectric, the present invention ferroelectric transistor can also be a metal-ferroelectric-metal (optional)-gate dielectric (optional)-semiconductive metal oxide FET.

摘要翻译： 本发明公开了一种采用半导体金属氧化物作为晶体管导电通道的新型晶体管结构。 通过用半导体金属氧化物沟道代替硅导电通道，晶体管可以实现更简单的制造工艺，并且可以实现3D结构以增加电路密度。 所公开的半导体金属氧化物晶体管可以在铁电非易失性存储器件中具有很大的潜力，具有与铁电材料良好的界面性质，与铁电层的可能的晶格匹配，减少或消除氧扩散问题以提高可靠性的另外的优点 铁电存储晶体管。 半导体金属氧化物膜优选是在晶体管工作条件下表现出半导体性质的金属氧化物，例如在二氧化铈或RuO 2 。 本发明的铁电晶体管可以是金属铁电半导体金属氧化物FET，其具有设置在设置在基板上的半导体金属氧化物沟道上的铁电层上的顶部金属电极的栅极堆叠。 使用附加的底部电极和栅极电介质层，本发明的铁电晶体管也可以是金属 - 铁电 - 金属（可选） - 门电介质（可选） - 导电金属氧化物FET。

公开(公告)号：US06664117B2

公开(公告)日：2003-12-16

申请号：US10256380

申请日：2002-09-26

申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  Jong-Jan Lee

发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  Jong-Jan Lee

IPC分类号： H01L2100

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  Y10S502/525

摘要： A method of forming a multi-layered, spin-coated perovskite thin film on a wafer includes preparing a perovskite precursor solution including mixing solid precursor material into acetic acid forming a mixed solution; heating the mixed solution in air for between about one hour to six hours; and filtering the solution when cooled; placing a wafer in a spin-coating mechanism; spinning the wafer at a speed of between about 500 rpm to 3500 rpm; injecting the precursor solution onto the wafer surface; baking the coated wafer at a temperature of between about 100° C. to 300° C.; annealing the coated wafer at a temperature of between about 400° C. to 650° C. in an oxygen atmosphere for between about two minutes to ten minutes; repeating the spinning, injecting, baking and annealing steps until a perovskite thin film of desired thickness is obtained; and annealing the perovskite thin film at a temperature of between about 500° C. to 750° C. in an oxygen atmosphere for between about ten minutes to two hours.

公开(公告)号：US5962884A

公开(公告)日：1999-10-05

申请号：US905380

申请日：1997-08-04

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/84 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223

摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of a fourth type. A FEM gate unit overlays the conductive channel of the third type. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.

摘要翻译： 在硅衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括将第一类型的掺杂杂质注入到衬底中以形成第一类型的导电沟道，将第二类型的掺杂杂质注入到 所述第一类型的导电沟道形成第二类型的导电沟道阱，在所述第二类型的导电沟道阱中注入第三类型的掺杂杂质以形成用作栅极结区域的第三类型的导电沟道， 在栅极结区域的任一侧上在第三类型的导电通道子阱中注入第四类型的掺杂杂质以形成用作源极结区域和漏极结区域的第四类型的多个导电沟道; 以及在栅极结区域上沉积FEM栅极单元。 铁电存储单元包括第一导电类型的硅衬底，形成在衬底中的第二导电类型的阱结构，形成在阱结构中的第三导电类型的结构，用作栅极结区域。 源极结区域和漏极结区域位于栅极结区域的任一侧的子阱中，被掺杂以形成第四类型的导电沟道。 FEM门单元覆盖第三类导电通道。 绝缘层覆盖了连接区域，FEM栅极单元和衬底。 合适的电极连接到存储单元中的各种有源区。

公开(公告)号：US5910673A

公开(公告)日：1999-06-08

申请号：US984801

申请日：1997-12-04

申请人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L23/62

CPC分类号： H01L27/0266 ,  Y10S438/981

摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

摘要翻译： 提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。 在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。 靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。 还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。

公开(公告)号：US07625787B2

公开(公告)日：2009-12-01

申请号：US11897691

申请日：2007-08-31

申请人： Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L29/78615 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/78624

摘要： A silicon (Si)-on-insulator (SOI) high voltage transistor with a body ground is provided with an associated fabrication process. The method provides a SOI substrate with a buried oxide (BOX) layer and a Si top layer having a first thickness and a second thickness, greater than the first thickness. A body ground is formed in the second thickness of Si top layer overlying the BOX layer. A control channel is formed in the first thickness of the Si top layer. A control gate is formed overlying the control channel. An auxiliary channel is formed in the second thickness of Si top layer partially overlying the body ground and extending into the first thickness of the Si top layer. An auxiliary gate is formed overlying the auxiliary channel. A pn junction is formed in the second thickness of Si top layer between the auxiliary channel and the body ground.

公开(公告)号：US20090219410A1

公开(公告)日：2009-09-03

申请号：US12039706

申请日：2008-02-28

申请人： Sheng Teng Hsu ,  Jong-Jan Lee

发明人： Sheng Teng Hsu ,  Jong-Jan Lee

IPC分类号： H04N5/235

CPC分类号： H04N5/3597 ,  H04N5/363

摘要： A complementary metal oxide semiconductor (CMOS) imager flush reset circuit is provided. The flush reset circuit has an interface to receive first (e.g., VDD) and second (e.g., ground) reference voltages. The flush reset circuit has a solitary (flush) signal interface. There is also an interface connected to a transistor set power interface to supply a Vflush1 signal at least one threshold voltage different than the second reference voltage, in response to receiving a flush signal. The flush signal is used to create a CMOS imager hard reset prior to a soft reset.

摘要翻译： 提供了互补金属氧化物半导体（CMOS）成像器冲洗复位电路。 闪光复位电路具有接收第一（例如VDD）和第二（例如，接地）参考电压的接口。 冲洗复位电路具有独立（齐平）信号接口。 响应于接收到刷新信号，还存在连接到晶体管集电源接口的接口，以向Vflush1信号提供不同于第二参考电压的至少一个阈值电压。 刷新信号用于在软复位之前创建CMOS成像器硬复位。

公开(公告)号：US20080290408A1

公开(公告)日：2008-11-27

申请号：US11805212

申请日：2007-05-22

申请人： Sheng Teng Hsu ,  Jong-Jan Lee

发明人： Sheng Teng Hsu ,  Jong-Jan Lee

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L29/0657 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/78624 ,  H01L29/78696

摘要： A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is formed in the thinned Si top layer area. The drain region is formed in an un-thinned area of the Si top layer. The channel has a first thickness adjacent the source region with first-type dopant, and a second thickness, greater than the first thickness, adjacent the drain region. The channel also has a sloped thickness between the first and second thicknesses. The second and sloped thicknesses have a second-type dopant, opposite of the first-type dopant. A stepped gate overlies the channel.

摘要翻译： 提供了一种制造具有阶梯式通道厚度的硅（Si）绝缘体（SOI）双扩散金属氧化物半导体晶体管（DMOST）的方法。 该方法提供具有表面的Si顶层的SOI衬底。 形成Si顶层的稀薄区域，并且在薄化的Si顶层区域中形成源极区域。 漏极区形成在Si顶层的未稀疏区域中。 沟道具有邻近源极区的第一厚度与第一类型掺杂物的第一厚度，以及大于第一厚度的与漏极区相邻的第二厚度。 通道在第一和第二厚度之间也具有倾斜的厚度。 第二和倾斜的厚度具有与第一类型掺杂剂相反的第二类型掺杂剂。 梯级门位于通道上。

公开(公告)号：US07193322B2

公开(公告)日：2007-03-20

申请号：US10985462

申请日：2004-11-09

申请人： Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823807

摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method forms a Si substrate with a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer. The method forms a strained-Si layer overlying the relaxed-SiGe layer; a silicon oxide layer overlying the strained-Si layer, a silicon nitride layer overlying the silicon oxide layer, and etches the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface. The method forms a sacrificial oxide liner on the STI trench surface. In response to forming the sacrificial oxide liner, the method rounds and reduces stress at the STI trench corners, removes the sacrificial oxide liner, and fills the STI trench with silicon oxide.

摘要翻译： 已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。 该方法形成具有覆盖Si衬底的松弛SiGe层或具有掩埋氧化物（BOX）层的绝缘体（SGOI）衬底的Si衬底的Si衬底。 该方法形成覆盖弛豫SiGe层的应变Si层; 覆盖应变Si层的氧化硅层，覆盖氧化硅层的氮化硅层，蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成STI沟槽 具有沟槽角和沟槽表面。 该方法在STI沟槽表面上形成牺牲氧化物衬垫。 响应于形成牺牲氧化物衬垫，该方法绕过并减小了STI沟槽角处的应力，去除牺牲氧化物衬垫，并用氧化硅填充STI沟槽。